From: David Brownell <david-b@pacbell.net>
To: "eric miao" <eric.y.miao@gmail.com>
Cc: "Linux Kernel list" <linux-kernel@vger.kernel.org>,
"Felipe Balbi" <felipebalbi@users.sourceforge.net>,
"Bill Gatliff" <bgat@billgatliff.com>,
"Haavard Skinnemoen" <hskinnemoen@atmel.com>,
"Andrew Victor" <andrew@sanpeople.com>,
"Tony Lindgren" <tony@atomide.com>,
"Jean Delvare" <khali@linux-fr.org>,
"Kevin Hilman" <khilman@mvista.com>,
"Paul Mundt" <lethal@linux-sh.org>,
"Ben Dooks" <ben@trinity.fluff.org>
Subject: Re: [patch/rfc 1/4] GPIO implementation framework
Date: Tue, 13 Nov 2007 11:06:10 -0800 [thread overview]
Message-ID: <200711131106.11277.david-b@pacbell.net> (raw)
In-Reply-To: <f17812d70711121828k49fe25b4ycf538061d0fb33b4@mail.gmail.com>
On Monday 12 November 2007, eric miao wrote:
> Hi David,
>
> I hope I was not late giving my humble feedback on this framework :-)
>
> Can we use "per gpio based" structure instead of "per gpio_chip" based one,
> just like what the generic IRQ layer is doing nowadays?
We "can" do most anything. What would that improve though?
Each irq_chip handles multiple IRQs ... just like this patch
has each gpio_chip handling multiple GPIOs. (Not that I think
GPIO code should closely model IRQ code; they need to address
very different problems.)
I can't tell what you intend to suggest as a "per-GPIO" data
structure; since I can think of at least three different ways
to do such a thing, you should be more concrete. I'd think it
should be in *addition* to a gpio_chip structure though.
> So that
>
> a. you don't have to declare per gpio_chip "can_sleep", "is_out" and
> "requested".
> Those will be just bits of properties of a single GPIO.
The can_sleep value is a per-controller thing. The other bits are
indeed per-GPIO.
So do you mean a structure with two bits, plus a pointer to a
gpio_chip, plus likely other stuff (what?) to make it work?
What would the hot-path costs be (for getting/setting values of
an on-chip GPIO)?
> b. and furthur more, one can avoid the use of ARCH_GPIOS_PER_CHIP, which
> leads to many holes
Why should holes (in the GPIO number sequence) be a problem? In
this code, they don't cost much space at all. They'd cost more
if there were a per-GPIO structure though...
The only downside of GPIOS_PER_CHIP that I know of right now
is that it complicates mixing gpio bank sizes; it's a ceiling,
some controllers would allocate more than they need. The
upside of that is efficiency, and a closer match to how
underlying hardware works.
Of course, GPIOS_PER_CHIP *could* be decoupled from how the
table of gpio_chip pointers is managed. If the table were to
group GPIOs in units of 8, a gpio_chip with 32 GPIOs could
take four adjacent entries while an 8-bit GPIO expander could
take just one. That'd be a very easy patch, supporting a more
dense allocation of GPIO numbers... although it would increase
static memory consumption by typically NR_GPIOS/4 pointers.
> c. gpio_to_chip() will be made easy and straight forward
I'd say "return chips[gpio / ARCH_GPIOS_PER_CHIP]" already meets
both criteria!
There's also "efficient" to consider; this way doesn't cost much
memory or add levels of indirection (compared to most platforms,
which already use a similar array).
> d. granularity of spin_lock()/_unlock() can be made small
> (per GPIO instead of per gpio_chip)
Why would per-GPIO locking be needed though? Look again...
The locking is there fundamentally because gpio_chip structures
may need to be unregistered; that's not a per-gpio issue.
Even when a gpio is marked in chip->requested under that lock,
that's part of ensuring that the unregistration is prevented so
long as the GPIO is in active use.
Plus, fine grained locking is rarely a good idea; it normally
increases locking overhead by involving multiple locks. Only
add extra locks if a single lock sees too much contention; and
even then, only if that contention can't be removed by using a
smarter design.
- Dave
> What do you think?
>
> - eric
>
> On Nov 6, 2007 5:05 AM, David Brownell <david-b@pacbell.net> wrote:
> > On Monday 29 October 2007, David Brownell wrote:
> > >
> > > Provides new implementation infrastructure that platforms may choose to use
> > > when implementing the GPIO programming interface. Platforms can update their
> > > GPIO support to use this. The downside is slower access to non-inlined GPIOs;
> > > rarely a problem except when bitbanging some protocol.
> >
> > I was asked just what that overhead *is* ... and it surprised me.
> > A summary of the results is appended to this note.
> >
> > Fortuntely it turns out those problems all go away if the gpiolib
> > code uses a *raw* spinlock to guard its table lookups. With a raw
> > spinlock, any performance impact of gpiolib seems to be well under
> > a microsecond in this bitbang context (and not objectionable).
> > Preempt became free; enabling debug options had only a minor cost.
> >
> > That's as it should be, since the only substantive changes were to
> > grab and release a lock, do one table lookup a bit differently, and
> > add one indirection function call ... changes which should not have
> > any visible performance impact on per-bit codepaths, and one might
> > expect to cost on the order of one dozen instructions.
> >
> >
> > So the next version of this code will include a few minor bugfixes,
> > and will also use a raw spinlock to protect that table. A raw lock
> > seems appropriate there in any case, since non-sleeping GPIOs should
> > be accessible from hardirq contexts even on RT kernels.
> >
> > If anyone has any strong arguments against using a raw spinlock
> > to protect that table, it'd be nice to know them sooner rather
> > than later.
> >
> > - Dave
> >
>
next prev parent reply other threads:[~2007-11-13 19:06 UTC|newest]
Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <200710291809.29936.david-b@pacbell.net>
2007-10-30 1:51 ` [patch/rfc 1/4] GPIO implementation framework David Brownell
2007-11-05 21:05 ` David Brownell
2007-11-13 2:28 ` eric miao
2007-11-13 19:06 ` David Brownell [this message]
2007-11-14 0:57 ` eric miao
2007-11-14 1:00 ` eric miao
2007-11-14 1:02 ` eric miao
2007-11-14 1:03 ` eric miao
2007-11-14 1:04 ` eric miao
2007-11-14 1:04 ` eric miao
2007-11-14 4:36 ` David Brownell
2007-11-14 6:51 ` eric miao
2007-11-14 7:19 ` David Brownell
2007-11-14 7:36 ` eric miao
2007-11-17 10:38 ` Jean Delvare
2007-11-17 17:36 ` David Brownell
2007-11-20 15:20 ` Jean Delvare
2007-11-14 4:18 ` David Brownell
2007-11-14 6:46 ` eric miao
2007-11-14 3:28 ` David Brownell
2007-11-14 3:25 ` David Brownell
2007-11-14 3:53 ` David Brownell
2007-11-14 6:37 ` eric miao
2007-11-14 3:30 ` David Brownell
2007-11-14 6:40 ` eric miao
2007-11-14 7:08 ` David Brownell
2007-11-27 1:46 ` David Brownell
2007-11-27 10:58 ` eric miao
2007-11-27 17:26 ` David Brownell
2007-11-27 19:03 ` David Brownell
2007-11-27 19:29 ` David Brownell
2007-11-28 5:11 ` eric miao
2007-11-28 3:15 ` [patch/rfc 2.6.24-rc3-mm] gpiolib grows a gpio_desc David Brownell
2007-11-28 9:10 ` eric miao
2007-11-28 9:53 ` David Brownell
2007-10-30 1:51 ` [patch/rfc 2/4] pcf875x I2C GPIO expander driver David Brownell
2007-11-30 12:32 ` Jean Delvare
2007-11-30 13:04 ` Bill Gatliff
2007-11-30 13:36 ` Jean Delvare
2007-11-30 14:09 ` Bill Gatliff
2007-11-30 18:40 ` David Brownell
2007-11-30 20:13 ` Jean Delvare
2007-11-30 20:59 ` David Brownell
2008-04-04 2:06 ` Trent Piepho
2008-04-04 2:45 ` Ben Nizette
2008-04-04 3:33 ` Trent Piepho
2008-04-04 4:57 ` Ben Nizette
2008-04-05 4:05 ` userspace GPIO access (WAS: [patch/rfc 2/4] pcf875x ...) David Brownell
2008-04-07 17:56 ` Trent Piepho
2008-04-04 8:09 ` [patch/rfc 2/4] pcf875x I2C GPIO expander driver Jean Delvare
2008-04-04 19:07 ` Trent Piepho
2008-04-04 19:36 ` Jean Delvare
2008-04-04 20:18 ` Trent Piepho
2008-04-05 2:51 ` David Brownell
2008-04-05 2:53 ` David Brownell
2007-12-06 3:03 ` [patch/rfc 2/4] pcf857x " David Brownell
2007-12-06 23:17 ` Jean Delvare
2007-12-07 4:02 ` David Brownell
2007-10-30 1:53 ` [patch/rfc 3/4] DaVinci platform uses new GPIOLIB David Brownell
2007-10-30 1:54 ` [patch/rfc 4/4] DaVinci EVM uses pcf857x GPIO driver David Brownell
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