Re: [PATCH -v2] x86, pci: Handle fallout pci devices with peer root bus

[Bjorn Helgaas <bjorn.helgaas@hp.com>]

On Monday, June 14, 2010 12:55:44 pm Yinghai Lu wrote:
> On 06/14/2010 11:39 AM, H. Peter Anvin wrote:
> > On 06/14/2010 11:34 AM, Bjorn Helgaas wrote:
> >>
> >> I made the point there that an HT chain may contain multiple HT/PCI
> >> host bridges, but you are stuck on the idea that "one HT chain == one
> >> PCI root bus."
> 
> should be.
> 
> >> I have not found the "one PCI host bridge per HT chain" requirement
> >> in the HT spec (if you find it, please point me to it).
> 
> according to my experience with LinuxBIOS. AMD chipset, nvidia and serverworks (broadcom)

I'm afraid I'm still not convinced.

> >> If an HT chain may contain multiple HT/PCI host bridges, then it's
> >> obvious that the HT host bridge registers read by amd_bus.c don't
> >> contain enough information to correctly assign address space to the
> >> PCI root buses.
> 
> the host bridges is on AMD CPUs, 

Don't confuse the HT host bridge with the PCI host bridge.  The HT I/O spec
is quite clear that it uses "host bridge" to refer to the HT host bridge,
i.e., the interface between CPUs and a HyperTransport link.

I agree that the *HT host bridge* is indeed on the AMD CPU.  But that is
certainly not the same as the PCI host bridge that bridges between an HT
link and a PCI bus.

See sections 4.9.4 (HT host bridge) and 7.4 (HT/PCI host bridge), for
example.

Bjorn