Re: [PATCH 1/4] perf: Add memory load/store events generic code

From: Anton Blanchard <anton@samba.org>
To: Peter Zijlstra <peterz@infradead.org>
Cc: Paul Mackerras <paulus@samba.org>,
	Lin Ming <ming.m.lin@intel.com>, Ingo Molnar <mingo@elte.hu>,
	Andi Kleen <andi@firstfloor.org>,
	Stephane Eranian <eranian@google.com>,
	Arnaldo Carvalho de Melo <acme@ghostprotocols.net>,
	linux-kernel <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 1/4] perf: Add memory load/store events generic code
Date: Fri, 8 Jul 2011 17:18:36 +1000	[thread overview]
Message-ID: <20110708171836.6465a12e@kryten> (raw)
In-Reply-To: <1309960718.3282.289.camel@twins>

Hi Peter,

> The thing we're talking about is Intel PEBS Load Latency/Precise Store
> and AMD IBS where together with a mem op retired event (mem loads
> retired for Load-Latency, mem stores retired for Precise Store)
> provides an additional field describing where the load/store was
> sourced from.
> 
> Such additional data would require the addition of a
> PERF_SAMPLE_SOURCE field or similar, for some reason or other I was
> under the impression some of the PPC chips had something similar. But
> if not, it saves us having to worry about that.

It does sound a lot like our event vector, where we can have up to
64 bits of information that goes with a sample. A lot of the fields
relate to loads and stores, but there are other fields (eg pipeline
information at the point the sample was taken).

So we could definitely use a field to capture this.

Anton