* [PATCH 0/2] PCI: PRI/PASSID cleanup and fix
@ 2011-11-11 17:06 Alex Williamson
2011-11-11 17:06 ` [PATCH 1/2] PCI: Enable is not exposed as a PASID capability Alex Williamson
` (2 more replies)
0 siblings, 3 replies; 9+ messages in thread
From: Alex Williamson @ 2011-11-11 17:06 UTC (permalink / raw)
To: linux-pci; +Cc: linux-kernel, jbarnes, joerg.roedel, bhelgaas
As suggested by Joerg, here's a split patch, separating a bug
fix in the PASID code incorrectly using a reserved bit in
the capability register from the renaming consistency changes
that found the bug. Thanks,
Alex
---
Alex Williamson (2):
PCI: More PRI/PASID cleanup
PCI: Enable is not exposed as a PASID capability
drivers/pci/ats.c | 70 +++++++++++++++++++++++-----------------------
include/linux/pci_regs.h | 30 +++++++++++---------
2 files changed, 51 insertions(+), 49 deletions(-)
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 1/2] PCI: Enable is not exposed as a PASID capability
2011-11-11 17:06 [PATCH 0/2] PCI: PRI/PASSID cleanup and fix Alex Williamson
@ 2011-11-11 17:06 ` Alex Williamson
2011-11-11 17:07 ` [PATCH 2/2] PCI: More PRI/PASID cleanup Alex Williamson
2011-11-23 10:47 ` [PATCH 0/2] PCI: PRI/PASSID cleanup and fix Joerg Roedel
2 siblings, 0 replies; 9+ messages in thread
From: Alex Williamson @ 2011-11-11 17:06 UTC (permalink / raw)
To: linux-pci; +Cc: linux-kernel, jbarnes, joerg.roedel, bhelgaas
The PASID ECN indicates bit 0 is reserved in the capability register.
Switch pci_enable_pasid() to error if PASID is already enabled and
don't expose enable as a feature in pci_pasid_features().
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
---
drivers/pci/ats.c | 5 ++---
1 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/ats.c b/drivers/pci/ats.c
index 831e192..8e95a12 100644
--- a/drivers/pci/ats.c
+++ b/drivers/pci/ats.c
@@ -348,7 +348,7 @@ int pci_enable_pasid(struct pci_dev *pdev, int features)
pci_read_config_word(pdev, pos + PCI_PASID_CONTROL_OFF, &control);
pci_read_config_word(pdev, pos + PCI_PASID_CAP_OFF, &supported);
- if (!(supported & PCI_PASID_ENABLE))
+ if (control & PCI_PASID_ENABLE)
return -EINVAL;
supported &= PCI_PASID_EXEC | PCI_PASID_PRIV;
@@ -390,7 +390,6 @@ EXPORT_SYMBOL_GPL(pci_disable_pasid);
* Returns a negative value when no PASI capability is present.
* Otherwise is returns a bitmask with supported features. Current
* features reported are:
- * PCI_PASID_ENABLE - PASID capability can be enabled
* PCI_PASID_EXEC - Execute permission supported
* PCI_PASID_PRIV - Priviledged mode supported
*/
@@ -405,7 +404,7 @@ int pci_pasid_features(struct pci_dev *pdev)
pci_read_config_word(pdev, pos + PCI_PASID_CAP_OFF, &supported);
- supported &= PCI_PASID_ENABLE | PCI_PASID_EXEC | PCI_PASID_PRIV;
+ supported &= PCI_PASID_EXEC | PCI_PASID_PRIV;
return supported;
}
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 2/2] PCI: More PRI/PASID cleanup
2011-11-11 17:06 [PATCH 0/2] PCI: PRI/PASSID cleanup and fix Alex Williamson
2011-11-11 17:06 ` [PATCH 1/2] PCI: Enable is not exposed as a PASID capability Alex Williamson
@ 2011-11-11 17:07 ` Alex Williamson
2011-11-11 17:40 ` Jesse Barnes
2011-11-23 10:47 ` [PATCH 0/2] PCI: PRI/PASSID cleanup and fix Joerg Roedel
2 siblings, 1 reply; 9+ messages in thread
From: Alex Williamson @ 2011-11-11 17:07 UTC (permalink / raw)
To: linux-pci; +Cc: linux-kernel, jbarnes, joerg.roedel, bhelgaas
More consistency cleanups. Drop the _OFF, separate and indent
CTRL/CAP/STATUS bit definitions. This helped find the previous
mis-use of bit 0 in the PASID capability register.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
---
drivers/pci/ats.c | 69 +++++++++++++++++++++++-----------------------
include/linux/pci_regs.h | 30 +++++++++++---------
2 files changed, 51 insertions(+), 48 deletions(-)
diff --git a/drivers/pci/ats.c b/drivers/pci/ats.c
index 8e95a12..2df49af 100644
--- a/drivers/pci/ats.c
+++ b/drivers/pci/ats.c
@@ -178,17 +178,18 @@ int pci_enable_pri(struct pci_dev *pdev, u32 reqs)
if (!pos)
return -EINVAL;
- pci_read_config_word(pdev, pos + PCI_PRI_CONTROL_OFF, &control);
- pci_read_config_word(pdev, pos + PCI_PRI_STATUS_OFF, &status);
- if ((control & PCI_PRI_ENABLE) || !(status & PCI_PRI_STATUS_STOPPED))
+ pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
+ pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
+ if ((control & PCI_PRI_CTRL_ENABLE) ||
+ !(status & PCI_PRI_STATUS_STOPPED))
return -EBUSY;
- pci_read_config_dword(pdev, pos + PCI_PRI_MAX_REQ_OFF, &max_requests);
+ pci_read_config_dword(pdev, pos + PCI_PRI_MAX_REQ, &max_requests);
reqs = min(max_requests, reqs);
- pci_write_config_dword(pdev, pos + PCI_PRI_ALLOC_REQ_OFF, reqs);
+ pci_write_config_dword(pdev, pos + PCI_PRI_ALLOC_REQ, reqs);
- control |= PCI_PRI_ENABLE;
- pci_write_config_word(pdev, pos + PCI_PRI_CONTROL_OFF, control);
+ control |= PCI_PRI_CTRL_ENABLE;
+ pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
return 0;
}
@@ -209,9 +210,9 @@ void pci_disable_pri(struct pci_dev *pdev)
if (!pos)
return;
- pci_read_config_word(pdev, pos + PCI_PRI_CONTROL_OFF, &control);
- control &= ~PCI_PRI_ENABLE;
- pci_write_config_word(pdev, pos + PCI_PRI_CONTROL_OFF, control);
+ pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
+ control &= ~PCI_PRI_CTRL_ENABLE;
+ pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
}
EXPORT_SYMBOL_GPL(pci_disable_pri);
@@ -230,9 +231,9 @@ bool pci_pri_enabled(struct pci_dev *pdev)
if (!pos)
return false;
- pci_read_config_word(pdev, pos + PCI_PRI_CONTROL_OFF, &control);
+ pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
- return (control & PCI_PRI_ENABLE) ? true : false;
+ return (control & PCI_PRI_CTRL_ENABLE) ? true : false;
}
EXPORT_SYMBOL_GPL(pci_pri_enabled);
@@ -252,13 +253,13 @@ int pci_reset_pri(struct pci_dev *pdev)
if (!pos)
return -EINVAL;
- pci_read_config_word(pdev, pos + PCI_PRI_CONTROL_OFF, &control);
- if (control & PCI_PRI_ENABLE)
+ pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
+ if (control & PCI_PRI_CTRL_ENABLE)
return -EBUSY;
- control |= PCI_PRI_RESET;
+ control |= PCI_PRI_CTRL_RESET;
- pci_write_config_word(pdev, pos + PCI_PRI_CONTROL_OFF, control);
+ pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
return 0;
}
@@ -285,10 +286,10 @@ bool pci_pri_stopped(struct pci_dev *pdev)
if (!pos)
return true;
- pci_read_config_word(pdev, pos + PCI_PRI_CONTROL_OFF, &control);
- pci_read_config_word(pdev, pos + PCI_PRI_STATUS_OFF, &status);
+ pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
+ pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
- if (control & PCI_PRI_ENABLE)
+ if (control & PCI_PRI_CTRL_ENABLE)
return false;
return (status & PCI_PRI_STATUS_STOPPED) ? true : false;
@@ -314,11 +315,11 @@ int pci_pri_status(struct pci_dev *pdev)
if (!pos)
return -EINVAL;
- pci_read_config_word(pdev, pos + PCI_PRI_CONTROL_OFF, &control);
- pci_read_config_word(pdev, pos + PCI_PRI_STATUS_OFF, &status);
+ pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
+ pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
/* Stopped bit is undefined when enable == 1, so clear it */
- if (control & PCI_PRI_ENABLE)
+ if (control & PCI_PRI_CTRL_ENABLE)
status &= ~PCI_PRI_STATUS_STOPPED;
return status;
@@ -345,21 +346,21 @@ int pci_enable_pasid(struct pci_dev *pdev, int features)
if (!pos)
return -EINVAL;
- pci_read_config_word(pdev, pos + PCI_PASID_CONTROL_OFF, &control);
- pci_read_config_word(pdev, pos + PCI_PASID_CAP_OFF, &supported);
+ pci_read_config_word(pdev, pos + PCI_PASID_CTRL, &control);
+ pci_read_config_word(pdev, pos + PCI_PASID_CAP, &supported);
- if (control & PCI_PASID_ENABLE)
+ if (control & PCI_PASID_CTRL_ENABLE)
return -EINVAL;
- supported &= PCI_PASID_EXEC | PCI_PASID_PRIV;
+ supported &= PCI_PASID_CAP_EXEC | PCI_PASID_CAP_PRIV;
/* User wants to enable anything unsupported? */
if ((supported & features) != features)
return -EINVAL;
- control = PCI_PASID_ENABLE | features;
+ control = PCI_PASID_CTRL_ENABLE | features;
- pci_write_config_word(pdev, pos + PCI_PASID_CONTROL_OFF, control);
+ pci_write_config_word(pdev, pos + PCI_PASID_CTRL, control);
return 0;
}
@@ -379,7 +380,7 @@ void pci_disable_pasid(struct pci_dev *pdev)
if (!pos)
return;
- pci_write_config_word(pdev, pos + PCI_PASID_CONTROL_OFF, control);
+ pci_write_config_word(pdev, pos + PCI_PASID_CTRL, control);
}
EXPORT_SYMBOL_GPL(pci_disable_pasid);
@@ -390,8 +391,8 @@ EXPORT_SYMBOL_GPL(pci_disable_pasid);
* Returns a negative value when no PASI capability is present.
* Otherwise is returns a bitmask with supported features. Current
* features reported are:
- * PCI_PASID_EXEC - Execute permission supported
- * PCI_PASID_PRIV - Priviledged mode supported
+ * PCI_PASID_CAP_EXEC - Execute permission supported
+ * PCI_PASID_CAP_PRIV - Priviledged mode supported
*/
int pci_pasid_features(struct pci_dev *pdev)
{
@@ -402,9 +403,9 @@ int pci_pasid_features(struct pci_dev *pdev)
if (!pos)
return -EINVAL;
- pci_read_config_word(pdev, pos + PCI_PASID_CAP_OFF, &supported);
+ pci_read_config_word(pdev, pos + PCI_PASID_CAP, &supported);
- supported &= PCI_PASID_EXEC | PCI_PASID_PRIV;
+ supported &= PCI_PASID_CAP_EXEC | PCI_PASID_CAP_PRIV;
return supported;
}
@@ -428,7 +429,7 @@ int pci_max_pasids(struct pci_dev *pdev)
if (!pos)
return -EINVAL;
- pci_read_config_word(pdev, pos + PCI_PASID_CAP_OFF, &supported);
+ pci_read_config_word(pdev, pos + PCI_PASID_CAP, &supported);
supported = (supported & PASID_NUMBER_MASK) >> PASID_NUMBER_SHIFT;
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
index 090d3a9..28fe380 100644
--- a/include/linux/pci_regs.h
+++ b/include/linux/pci_regs.h
@@ -666,22 +666,24 @@
#define PCI_ATS_MIN_STU 12 /* shift of minimum STU block */
/* Page Request Interface */
-#define PCI_PRI_CONTROL_OFF 0x04 /* Offset of control register */
-#define PCI_PRI_STATUS_OFF 0x06 /* Offset of status register */
-#define PCI_PRI_ENABLE 0x0001 /* Enable mask */
-#define PCI_PRI_RESET 0x0002 /* Reset bit mask */
-#define PCI_PRI_STATUS_RF 0x0001 /* Request Failure */
-#define PCI_PRI_STATUS_UPRGI 0x0002 /* Unexpected PRG index */
-#define PCI_PRI_STATUS_STOPPED 0x0100 /* PRI Stopped */
-#define PCI_PRI_MAX_REQ_OFF 0x08 /* Cap offset for max reqs supported */
-#define PCI_PRI_ALLOC_REQ_OFF 0x0c /* Cap offset for max reqs allowed */
+#define PCI_PRI_CTRL 0x04 /* PRI control register */
+#define PCI_PRI_CTRL_ENABLE 0x01 /* Enable */
+#define PCI_PRI_CTRL_RESET 0x02 /* Reset */
+#define PCI_PRI_STATUS 0x06 /* PRI status register */
+#define PCI_PRI_STATUS_RF 0x001 /* Response Failure */
+#define PCI_PRI_STATUS_UPRGI 0x002 /* Unexpected PRG index */
+#define PCI_PRI_STATUS_STOPPED 0x100 /* PRI Stopped */
+#define PCI_PRI_MAX_REQ 0x08 /* PRI max reqs supported */
+#define PCI_PRI_ALLOC_REQ 0x0c /* PRI max reqs allowed */
/* PASID capability */
-#define PCI_PASID_CAP_OFF 0x04 /* PASID feature register */
-#define PCI_PASID_CONTROL_OFF 0x06 /* PASID control register */
-#define PCI_PASID_ENABLE 0x01 /* Enable/Supported bit */
-#define PCI_PASID_EXEC 0x02 /* Exec permissions Enable/Supported */
-#define PCI_PASID_PRIV 0x04 /* Priviledge Mode Enable/Support */
+#define PCI_PASID_CAP 0x04 /* PASID feature register */
+#define PCI_PASID_CAP_EXEC 0x02 /* Exec permissions Supported */
+#define PCI_PASID_CAP_PRIV 0x04 /* Priviledge Mode Supported */
+#define PCI_PASID_CTRL 0x06 /* PASID control register */
+#define PCI_PASID_CTRL_ENABLE 0x01 /* Enable bit */
+#define PCI_PASID_CTRL_EXEC 0x02 /* Exec permissions Enable */
+#define PCI_PASID_CTRL_PRIV 0x04 /* Priviledge Mode Enable */
/* Single Root I/O Virtualization */
#define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] PCI: More PRI/PASID cleanup
2011-11-11 17:07 ` [PATCH 2/2] PCI: More PRI/PASID cleanup Alex Williamson
@ 2011-11-11 17:40 ` Jesse Barnes
0 siblings, 0 replies; 9+ messages in thread
From: Jesse Barnes @ 2011-11-11 17:40 UTC (permalink / raw)
To: Alex Williamson; +Cc: linux-pci, linux-kernel, joerg.roedel, bhelgaas
[-- Attachment #1: Type: text/plain, Size: 489 bytes --]
On Fri, 11 Nov 2011 10:07:36 -0700
Alex Williamson <alex.williamson@redhat.com> wrote:
> More consistency cleanups. Drop the _OFF, separate and indent
> CTRL/CAP/STATUS bit definitions. This helped find the previous
> mis-use of bit 0 in the PASID capability register.
>
> Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
> ---
Thanks Alex; Joerg I'll wait for your r-b and tested-bys on these.
Thanks,
--
Jesse Barnes, Intel Open Source Technology Center
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 0/2] PCI: PRI/PASSID cleanup and fix
2011-11-11 17:06 [PATCH 0/2] PCI: PRI/PASSID cleanup and fix Alex Williamson
2011-11-11 17:06 ` [PATCH 1/2] PCI: Enable is not exposed as a PASID capability Alex Williamson
2011-11-11 17:07 ` [PATCH 2/2] PCI: More PRI/PASID cleanup Alex Williamson
@ 2011-11-23 10:47 ` Joerg Roedel
2011-11-23 22:45 ` Jesse Barnes
2 siblings, 1 reply; 9+ messages in thread
From: Joerg Roedel @ 2011-11-23 10:47 UTC (permalink / raw)
To: Alex Williamson; +Cc: linux-pci, linux-kernel, jbarnes, bhelgaas
On Fri, Nov 11, 2011 at 10:06:23AM -0700, Alex Williamson wrote:
> Alex Williamson (2):
> PCI: More PRI/PASID cleanup
> PCI: Enable is not exposed as a PASID capability
For both:
Reviewed-by: Joerg Roedel <joerg.roedel@amd.com>
Tested-by: Joerg Roedel <joerg.roedel@amd.com>
--
AMD Operating System Research Center
Advanced Micro Devices GmbH Einsteinring 24 85609 Dornach
General Managers: Alberto Bozzo, Andrew Bowd
Registration: Dornach, Landkr. Muenchen; Registerger. Muenchen, HRB Nr. 43632
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 0/2] PCI: PRI/PASSID cleanup and fix
2011-11-23 10:47 ` [PATCH 0/2] PCI: PRI/PASSID cleanup and fix Joerg Roedel
@ 2011-11-23 22:45 ` Jesse Barnes
2011-11-28 10:40 ` Joerg Roedel
0 siblings, 1 reply; 9+ messages in thread
From: Jesse Barnes @ 2011-11-23 22:45 UTC (permalink / raw)
To: Joerg Roedel; +Cc: Alex Williamson, linux-pci, linux-kernel, bhelgaas
[-- Attachment #1: Type: text/plain, Size: 517 bytes --]
On Wed, 23 Nov 2011 11:47:05 +0100
Joerg Roedel <joerg.roedel@amd.com> wrote:
> On Fri, Nov 11, 2011 at 10:06:23AM -0700, Alex Williamson wrote:
> > Alex Williamson (2):
> > PCI: More PRI/PASID cleanup
> > PCI: Enable is not exposed as a PASID capability
>
> For both:
>
> Reviewed-by: Joerg Roedel <joerg.roedel@amd.com>
> Tested-by: Joerg Roedel <joerg.roedel@amd.com>
Ok, thanks guys. I'll queue these up after Thanksgiving.
--
Jesse Barnes, Intel Open Source Technology Center
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 836 bytes --]
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 0/2] PCI: PRI/PASSID cleanup and fix
2011-11-23 22:45 ` Jesse Barnes
@ 2011-11-28 10:40 ` Joerg Roedel
2011-12-05 18:24 ` Jesse Barnes
0 siblings, 1 reply; 9+ messages in thread
From: Joerg Roedel @ 2011-11-28 10:40 UTC (permalink / raw)
To: Jesse Barnes; +Cc: Alex Williamson, linux-pci, linux-kernel, bhelgaas
On Wed, Nov 23, 2011 at 02:45:10PM -0800, Jesse Barnes wrote:
> On Wed, 23 Nov 2011 11:47:05 +0100
> Joerg Roedel <joerg.roedel@amd.com> wrote:
>
> > On Fri, Nov 11, 2011 at 10:06:23AM -0700, Alex Williamson wrote:
> > > Alex Williamson (2):
> > > PCI: More PRI/PASID cleanup
> > > PCI: Enable is not exposed as a PASID capability
> >
> > For both:
> >
> > Reviewed-by: Joerg Roedel <joerg.roedel@amd.com>
> > Tested-by: Joerg Roedel <joerg.roedel@amd.com>
>
> Ok, thanks guys. I'll queue these up after Thanksgiving.
>
> --
> Jesse Barnes, Intel Open Source Technology Center
Great. Can you provide a seperate branch with these changes that I can
pull into my tree, please? I have upcoming changes that will conflict
with these patches. And I would like to solve them before merge.
Joerg
--
AMD Operating System Research Center
Advanced Micro Devices GmbH Einsteinring 24 85609 Dornach
General Managers: Alberto Bozzo, Andrew Bowd
Registration: Dornach, Landkr. Muenchen; Registerger. Muenchen, HRB Nr. 43632
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 0/2] PCI: PRI/PASSID cleanup and fix
2011-11-28 10:40 ` Joerg Roedel
@ 2011-12-05 18:24 ` Jesse Barnes
2011-12-06 10:05 ` Joerg Roedel
0 siblings, 1 reply; 9+ messages in thread
From: Jesse Barnes @ 2011-12-05 18:24 UTC (permalink / raw)
To: Joerg Roedel; +Cc: Alex Williamson, linux-pci, linux-kernel, bhelgaas
[-- Attachment #1: Type: text/plain, Size: 1112 bytes --]
On Mon, 28 Nov 2011 11:40:55 +0100
Joerg Roedel <joerg.roedel@amd.com> wrote:
> On Wed, Nov 23, 2011 at 02:45:10PM -0800, Jesse Barnes wrote:
> > On Wed, 23 Nov 2011 11:47:05 +0100
> > Joerg Roedel <joerg.roedel@amd.com> wrote:
> >
> > > On Fri, Nov 11, 2011 at 10:06:23AM -0700, Alex Williamson wrote:
> > > > Alex Williamson (2):
> > > > PCI: More PRI/PASID cleanup
> > > > PCI: Enable is not exposed as a PASID capability
> > >
> > > For both:
> > >
> > > Reviewed-by: Joerg Roedel <joerg.roedel@amd.com>
> > > Tested-by: Joerg Roedel <joerg.roedel@amd.com>
> >
> > Ok, thanks guys. I'll queue these up after Thanksgiving.
> >
> > --
> > Jesse Barnes, Intel Open Source Technology Center
>
> Great. Can you provide a seperate branch with these changes that I can
> pull into my tree, please? I have upcoming changes that will conflict
> with these patches. And I would like to solve them before merge.
Ok, I pushed these to a 'pri-changes' branch, which is a superset of my
current linux-next branch.
--
Jesse Barnes, Intel Open Source Technology Center
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 836 bytes --]
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 0/2] PCI: PRI/PASSID cleanup and fix
2011-12-05 18:24 ` Jesse Barnes
@ 2011-12-06 10:05 ` Joerg Roedel
0 siblings, 0 replies; 9+ messages in thread
From: Joerg Roedel @ 2011-12-06 10:05 UTC (permalink / raw)
To: Jesse Barnes; +Cc: Alex Williamson, linux-pci, linux-kernel, bhelgaas
On Mon, Dec 05, 2011 at 10:24:23AM -0800, Jesse Barnes wrote:
> On Mon, 28 Nov 2011 11:40:55 +0100
> Joerg Roedel <joerg.roedel@amd.com> wrote:
> > Great. Can you provide a seperate branch with these changes that I can
> > pull into my tree, please? I have upcoming changes that will conflict
> > with these patches. And I would like to solve them before merge.
>
> Ok, I pushed these to a 'pri-changes' branch, which is a superset of my
> current linux-next branch.
Great, thanks :)
--
AMD Operating System Research Center
Advanced Micro Devices GmbH Einsteinring 24 85609 Dornach
General Managers: Alberto Bozzo, Andrew Bowd
Registration: Dornach, Landkr. Muenchen; Registerger. Muenchen, HRB Nr. 43632
^ permalink raw reply [flat|nested] 9+ messages in thread
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2011-11-11 17:06 [PATCH 0/2] PCI: PRI/PASSID cleanup and fix Alex Williamson
2011-11-11 17:06 ` [PATCH 1/2] PCI: Enable is not exposed as a PASID capability Alex Williamson
2011-11-11 17:07 ` [PATCH 2/2] PCI: More PRI/PASID cleanup Alex Williamson
2011-11-11 17:40 ` Jesse Barnes
2011-11-23 10:47 ` [PATCH 0/2] PCI: PRI/PASSID cleanup and fix Joerg Roedel
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