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From: Arnd Bergmann <arnd.bergmann@linaro.org>
Organization: Linaro Limited 
To: Viresh Kumar <viresh.kumar@linaro.org>
Subject: Re: [PATCH] Fixes for dw_dmac and atmel-mci for AP700x
Date: Tue, 21 Aug 2012 08:34:53 +0000
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Cc: Hein Tibosch <hein_tibosch@yahoo.es>,
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On Tuesday 21 August 2012, Viresh Kumar wrote:
> On 21 August 2012 13:02, Hein Tibosch <hein_tibosch@yahoo.es> wrote:
> 
> > On 8/21/2012 2:35 PM, Viresh Kumar wrote:
> >
> > It got swapped as 0xAABB.CCDD => 0xCCDD.AABB
> >
> 
> @Arnd: How do we explain this? shouldn't it be DD CC BB AA??

Yes, this is very strange. Maybe the compiler already splits the
access into two 16-byte loads and that confuses the device?

> > Memory barriers: within the AVR32 code, one often sees explicit ways to
> > introduce memory barriers, e.g.:
> >
> >     hsmc_readl(hsmc, MODE0); /* I/O barrier */
> >
> 
> For ARM it has become a bit complex about using barriers. That's why they
> are added in readl/writel to remove any confusion.

To be more exact: the reason why readl/writel have the barriers is that
device drivers written for x86 expect the barrier semantics to be implied.
ARM also has readl_relaxed/writel_relaxed, which don't have a barrier
against DMA but still enforce ordering between the readl calls (implied
by the CPU architecture).

	Arnd