From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759691Ab2INRkh (ORCPT ); Fri, 14 Sep 2012 13:40:37 -0400 Received: from cam-admin0.cambridge.arm.com ([217.140.96.50]:47053 "EHLO cam-admin0.cambridge.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1759532Ab2INRkf (ORCPT ); Fri, 14 Sep 2012 13:40:35 -0400 Date: Fri, 14 Sep 2012 18:39:46 +0100 From: Catalin Marinas To: Arnd Bergmann Cc: Olof Johansson , "linux-arch@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , Will Deacon Subject: Re: [PATCH v2 13/31] arm64: Device specific operations Message-ID: <20120914173946.GE2927@arm.com> References: <1344966752-16102-1-git-send-email-catalin.marinas@arm.com> <20120815003355.GF19607@quad.lixom.net> <20120914172944.GB2927@arm.com> <201209141731.59938.arnd@arndb.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <201209141731.59938.arnd@arndb.de> User-Agent: Mutt/1.5.20 (2009-06-14) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Sep 14, 2012 at 06:31:59PM +0100, Arnd Bergmann wrote: > On Friday 14 September 2012, Catalin Marinas wrote: > > (revisiting unanswered emails :)) > > > > On Wed, Aug 15, 2012 at 01:33:55AM +0100, Olof Johansson wrote: > > > On Tue, Aug 14, 2012 at 06:52:14PM +0100, Catalin Marinas wrote: > > > > +/* > > > > + * I/O port access primitives. > > > > + */ > > > > +#define IO_SPACE_LIMIT 0xffff > > > > + > > > > +/* > > > > + * We currently don't have any platform with PCI support, so just leave this > > > > + * defined to 0 until needed. > > > > + */ > > > > +#define PCI_IOBASE ((void __iomem *)0) > > > > > > You could just leave out the PCI / I/O code alltogether instead. > > > > I would leave this in as some of the first platforms to appear will have > > PCIe. At some point we'll add a fixed address where the PCI_IOBASE is > > mapped. > > > > I guess the cleanest way would be to reserve a virtual memory region right away > and document it in the file where you describe the memory layout. Then you can > fill the value in here. Yes, easy to do. Any access will fault until we add the PCI support. -- Catalin