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Date: Thu, 7 Feb 2013 20:09:21 +0100
From: Ingo Molnar <mingo@kernel.org>
To: Jacob Shin <jacob.shin@amd.com>
Cc: Thomas Gleixner <tglx@linutronix.de>, Ingo Molnar <mingo@redhat.com>,
        "H. Peter Anvin" <hpa@zytor.com>, x86@kernel.org,
        Peter Zijlstra <a.p.zijlstra@chello.nl>,
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        Stephane Eranian <eranian@google.com>, Jiri Olsa <jolsa@redhat.com>,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH 6/6] perf, amd: Enable northbridge performance counters
 on AMD family 15h
Message-ID: <20130207190921.GC25223@gmail.com>
References: <1360171589-6381-1-git-send-email-jacob.shin@amd.com>
 <1360171589-6381-7-git-send-email-jacob.shin@amd.com>
 <20130207175703.GA3398@jshin-Toonie>
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* Jacob Shin <jacob.shin@amd.com> wrote:

> On Wed, Feb 06, 2013 at 11:26:29AM -0600, Jacob Shin wrote:
> > On AMD family 15h processors, there are 4 new performance counters
> > (in addition to 6 core performance counters) that can be used for
> > counting northbridge events (i.e. DRAM accesses). Their bit fields are
> > almost identical to the core performance counters. However, unlike the
> > core performance counters, these MSRs are shared between multiple
> > cores (that share the same northbridge). We will reuse the same code
> > path as existing family 10h northbridge event constraints handler
> > logic to enforce this sharing.
> > 
> > Signed-off-by: Jacob Shin <jacob.shin@amd.com>
> 
> Hi Ingo, could you please apply this one to tip as well? I 
> recieved tip-bot emails for all other patches in this series 
> except for this last one 6/6.
> 
> Or was that intentional? If so, what other changes are 
> required/ recommended?

Was waiting for Stephane's ack.

Thanks,

	Ingo