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From: Stephane Eranian <>
Subject: [PATCH] perf: fix comments in PERF_MEM_LVL bitmask
Date: Fri, 5 Apr 2013 16:49:41 +0200
Message-ID: <20130405144941.GA30503@quad> (raw)

This small patch fixes a mistake in the comments
for the PERF_MEM_LVL_* events. The L2, L3 bits simply
represent cache levels, not hits or misses. That is

Signed-off-by: Stephane Eranian <>

diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h
index 964a450..fb104e5 100644
--- a/include/uapi/linux/perf_event.h
+++ b/include/uapi/linux/perf_event.h
@@ -645,8 +645,8 @@ union perf_mem_data_src {
 #define PERF_MEM_LVL_MISS	0x04  /* miss level  */
 #define PERF_MEM_LVL_L1		0x08  /* L1 */
 #define PERF_MEM_LVL_LFB	0x10  /* Line Fill Buffer */
-#define PERF_MEM_LVL_L2		0x20  /* L2 hit */
-#define PERF_MEM_LVL_L3		0x40  /* L3 hit */
+#define PERF_MEM_LVL_L2		0x20  /* L2 */
+#define PERF_MEM_LVL_L3		0x40  /* L3 */
 #define PERF_MEM_LVL_LOC_RAM	0x80  /* Local DRAM */
 #define PERF_MEM_LVL_REM_RAM1	0x100 /* Remote DRAM (1 hop) */
 #define PERF_MEM_LVL_REM_RAM2	0x200 /* Remote DRAM (2 hops) */

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Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-04-05 14:49 Stephane Eranian [this message]
2013-04-08 15:33 ` [tip:perf/core] perf: Fix " tip-bot for Stephane Eranian

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