From: Gleb Natapov <gleb@redhat.com>
To: Andi Kleen <andi@firstfloor.org>
Cc: mingo@elte.hu, acme@redhat.com, linux-kernel@vger.kernel.org,
Andi Kleen <ak@linux.intel.com>
Subject: Re: [PATCH 08/15] perf, kvm: Support the intx/intx_cp modifiers in KVM arch perfmon emulation v5
Date: Tue, 23 Apr 2013 11:48:31 +0300 [thread overview]
Message-ID: <20130423084831.GF12401@redhat.com> (raw)
In-Reply-To: <1366485563-16209-9-git-send-email-andi@firstfloor.org>
On Sat, Apr 20, 2013 at 12:19:16PM -0700, Andi Kleen wrote:
> From: Andi Kleen <ak@linux.intel.com>
>
> This is not arch perfmon, but older CPUs will just ignore it. This makes
> it possible to do at least some TSX measurements from a KVM guest
>
> Cc: gleb@redhat.com
> v2: Various fixes to address review feedback
> v3: Ignore the bits when no CPUID. No #GP. Force raw events with TSX bits.
> v4: Use reserved bits for #GP
> v5: Remove obsolete argument
> Signed-off-by: Andi Kleen <ak@linux.intel.com>
Acked-by: Gleb Natapov <gleb@redhat.com>
> ---
> arch/x86/include/asm/kvm_host.h | 1 +
> arch/x86/kvm/pmu.c | 25 ++++++++++++++++++++-----
> 2 files changed, 21 insertions(+), 5 deletions(-)
>
> diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
> index 4979778..7c7e207 100644
> --- a/arch/x86/include/asm/kvm_host.h
> +++ b/arch/x86/include/asm/kvm_host.h
> @@ -315,6 +315,7 @@ struct kvm_pmu {
> u64 global_ovf_ctrl;
> u64 counter_bitmask[2];
> u64 global_ctrl_mask;
> + u64 reserved_bits;
> u8 version;
> struct kvm_pmc gp_counters[INTEL_PMC_MAX_GENERIC];
> struct kvm_pmc fixed_counters[INTEL_PMC_MAX_FIXED];
> diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c
> index cfc258a..9317c43 100644
> --- a/arch/x86/kvm/pmu.c
> +++ b/arch/x86/kvm/pmu.c
> @@ -160,7 +160,7 @@ static void stop_counter(struct kvm_pmc *pmc)
>
> static void reprogram_counter(struct kvm_pmc *pmc, u32 type,
> unsigned config, bool exclude_user, bool exclude_kernel,
> - bool intr)
> + bool intr, bool intx, bool intx_cp)
> {
> struct perf_event *event;
> struct perf_event_attr attr = {
> @@ -173,6 +173,10 @@ static void reprogram_counter(struct kvm_pmc *pmc, u32 type,
> .exclude_kernel = exclude_kernel,
> .config = config,
> };
> + if (intx)
> + attr.config |= HSW_INTX;
> + if (intx_cp)
> + attr.config |= HSW_INTX_CHECKPOINTED;
>
> attr.sample_period = (-pmc->counter) & pmc_bitmask(pmc);
>
> @@ -226,7 +230,9 @@ static void reprogram_gp_counter(struct kvm_pmc *pmc, u64 eventsel)
>
> if (!(eventsel & (ARCH_PERFMON_EVENTSEL_EDGE |
> ARCH_PERFMON_EVENTSEL_INV |
> - ARCH_PERFMON_EVENTSEL_CMASK))) {
> + ARCH_PERFMON_EVENTSEL_CMASK |
> + HSW_INTX |
> + HSW_INTX_CHECKPOINTED))) {
> config = find_arch_event(&pmc->vcpu->arch.pmu, event_select,
> unit_mask);
> if (config != PERF_COUNT_HW_MAX)
> @@ -239,7 +245,9 @@ static void reprogram_gp_counter(struct kvm_pmc *pmc, u64 eventsel)
> reprogram_counter(pmc, type, config,
> !(eventsel & ARCH_PERFMON_EVENTSEL_USR),
> !(eventsel & ARCH_PERFMON_EVENTSEL_OS),
> - eventsel & ARCH_PERFMON_EVENTSEL_INT);
> + eventsel & ARCH_PERFMON_EVENTSEL_INT,
> + (eventsel & HSW_INTX),
> + (eventsel & HSW_INTX_CHECKPOINTED));
> }
>
> static void reprogram_fixed_counter(struct kvm_pmc *pmc, u8 en_pmi, int idx)
> @@ -256,7 +264,7 @@ static void reprogram_fixed_counter(struct kvm_pmc *pmc, u8 en_pmi, int idx)
> arch_events[fixed_pmc_events[idx]].event_type,
> !(en & 0x2), /* exclude user */
> !(en & 0x1), /* exclude kernel */
> - pmi);
> + pmi, false, false);
> }
>
> static inline u8 fixed_en_pmi(u64 ctrl, int idx)
> @@ -400,7 +408,7 @@ int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
> } else if ((pmc = get_gp_pmc(pmu, index, MSR_P6_EVNTSEL0))) {
> if (data == pmc->eventsel)
> return 0;
> - if (!(data & 0xffffffff00200000ull)) {
> + if (!(data & pmu->reserved_bits)) {
> reprogram_gp_counter(pmc, data);
> return 0;
> }
> @@ -442,6 +450,7 @@ void kvm_pmu_cpuid_update(struct kvm_vcpu *vcpu)
> pmu->counter_bitmask[KVM_PMC_GP] = 0;
> pmu->counter_bitmask[KVM_PMC_FIXED] = 0;
> pmu->version = 0;
> + pmu->reserved_bits = 0xffffffff00200000ull;
>
> entry = kvm_find_cpuid_entry(vcpu, 0xa, 0);
> if (!entry)
> @@ -470,6 +479,12 @@ void kvm_pmu_cpuid_update(struct kvm_vcpu *vcpu)
> pmu->global_ctrl = ((1 << pmu->nr_arch_gp_counters) - 1) |
> (((1ull << pmu->nr_arch_fixed_counters) - 1) << INTEL_PMC_IDX_FIXED);
> pmu->global_ctrl_mask = ~pmu->global_ctrl;
> +
> + entry = kvm_find_cpuid_entry(vcpu, 7, 0);
> + if (entry &&
> + (boot_cpu_has(X86_FEATURE_HLE) || boot_cpu_has(X86_FEATURE_RTM)) &&
> + (entry->ebx & (X86_FEATURE_HLE|X86_FEATURE_RTM)))
> + pmu->reserved_bits ^= HSW_INTX|HSW_INTX_CHECKPOINTED;
> }
>
> void kvm_pmu_init(struct kvm_vcpu *vcpu)
> --
> 1.7.7.6
--
Gleb.
next prev parent reply other threads:[~2013-04-23 8:48 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-04-20 19:19 perf PMU support for Haswell v8 Andi Kleen
2013-04-20 19:19 ` [PATCH 01/15] perf, x86: Suppress duplicated abort LBR records Andi Kleen
2013-04-20 19:19 ` [PATCH 02/15] perf, x86: Disable software LBR filter for Sandy Bridge/Haswell Andi Kleen
2013-04-20 19:19 ` [PATCH 03/15] perf, x86: Support full width counting v3 Andi Kleen
2013-04-20 19:19 ` [PATCH 04/15] perf, tools: Support sorting by in_tx, abort branch flags v3 Andi Kleen
2013-04-20 19:19 ` [PATCH 05/15] perf, tools: Add abort_tx,no_tx,in_tx branch filter options to perf record -j v3 Andi Kleen
2013-04-20 19:19 ` [PATCH 06/15] perf, x86: Support the TSX intx/intx_cp qualifiers v4 Andi Kleen
2013-04-20 19:19 ` [PATCH 07/15] perf, x86: Avoid checkpointed counters causing excessive TSX aborts v4 Andi Kleen
2013-04-20 19:19 ` [PATCH 08/15] perf, kvm: Support the intx/intx_cp modifiers in KVM arch perfmon emulation v5 Andi Kleen
2013-04-23 8:48 ` Gleb Natapov [this message]
2013-04-20 19:19 ` [PATCH 09/15] perf, x86: Support PERF_SAMPLE_ADDR for all PEBS events v3 Andi Kleen
2013-04-20 19:19 ` [PATCH 10/15] perf, core: Add generic transaction flags v3 Andi Kleen
2013-04-20 19:19 ` [PATCH 11/15] perf, x86: Add Haswell specific transaction flag reporting Andi Kleen
2013-04-20 19:19 ` [PATCH 12/15] perf, tools: Add support for record transaction flags v3 Andi Kleen
2013-04-20 19:19 ` [PATCH 13/15] tools, perf: Add a precise event qualifier v2 Andi Kleen
2013-04-20 19:19 ` [PATCH 14/15] perf, x86: Add Haswell TSX event aliases v4 Andi Kleen
2013-04-20 19:19 ` [PATCH 15/15] perf, tools: Add perf stat --transaction v3 Andi Kleen
2013-06-19 8:51 ` Michael Ellerman
2013-06-19 14:46 ` Andi Kleen
2013-06-27 3:18 ` Michael Ellerman
2013-06-27 3:49 ` Andi Kleen
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20130423084831.GF12401@redhat.com \
--to=gleb@redhat.com \
--cc=acme@redhat.com \
--cc=ak@linux.intel.com \
--cc=andi@firstfloor.org \
--cc=linux-kernel@vger.kernel.org \
--cc=mingo@elte.hu \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).