Re: [PATCHv4 2/3] drivers: spi: Add qspi flash controller

[Felipe Balbi <balbi@ti.com>]

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Hi,

On Thu, Jul 18, 2013 at 02:18:22PM +0100, Mark Brown wrote:
> > >>+static irqreturn_t ti_qspi_isr(int irq, void *dev_id)
> > >>+{
> > >>+	struct ti_qspi *qspi = dev_id;
> > >>+	u16 mask, stat;
> > >>+
> > >>+	irqreturn_t ret = IRQ_HANDLED;
> > >>+
> > >>+	spin_lock(&qspi->lock);
> > >>+
> > >>+	stat = ti_qspi_readl(qspi, QSPI_SPI_STATUS_REG);
> > >>+	mask = ti_qspi_readl(qspi, QSPI_INTR_ENABLE_SET_REG);
> > >>+
> > >>+	if (stat&&  mask)
> > >>+		ret = IRQ_WAKE_THREAD;
> > >>+
> > >>+	spin_unlock(&qspi->lock);
> > >>+
> > >>+	return ret;
> 
> > >According to the above code we might interrupt for masked events...
> > >that's a bit worrying isn't it?
> 
> > Yes, there is WC interrupt enable bit which enables the interrupt.
> > This interrupt
> > gets disabled by writing to the CLEAR reg in the threaded irq.
> 
> So why do we report that we handled the interrupt then?  Shouldn't we at
> least warn if we're getting spurious IRQs?

not spurious. OMAP has two sets of IRQ status registers. One is call
IRQSTATUS$n (n = 0, 1, ...) and IRQSTATUS_RAW$n.

IRQSTATUS$n will only enable the bits which fired IRQs and aren't
masked while IRQSTATUS_RAW$n will also enable the bits which are masked.
I could never come up with a use case where we would need to handle IRQs
which we decided to mask, but perhaps there might be some cases, I don't
know.

Based on that, I believe Sourav is reading IRQSTATUS_RAW$n, then he need
to clear the masked bits.

-- 
balbi

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