From: Mark Brown <broonie@kernel.org>
To: Chew Chiau Ee <chiau.ee.chew@intel.com>
Cc: Eric Miao <eric.y.miao@gmail.com>,
Russell King <linux@arm.linux.org.uk>,
Haojian Zhuang <haojian.zhuang@gmail.com>,
linux-arm-kernel@lists.infradead.org, linux-spi@vger.kernel.org,
linux-kernel@vger.kernel.org,
Mika Westerberg <mika.westerberg@linux.intel.com>
Subject: Re: [PATCH] spi/pxa2xx: Restore private register bits.
Date: Thu, 28 Nov 2013 11:22:35 +0000 [thread overview]
Message-ID: <20131128112235.GA27568@sirena.org.uk> (raw)
In-Reply-To: <1385662391-27573-1-git-send-email-chiau.ee.chew@intel.com>
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On Fri, Nov 29, 2013 at 02:13:11AM +0800, Chew Chiau Ee wrote:
> From: Chew, Chiau Ee <chiau.ee.chew@intel.com>
>
> The Intel LPSS SPI private register bits have to be restored
> when system resume from S3 suspend.
Applied, thanks.
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prev parent reply other threads:[~2013-11-28 11:23 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-11-28 18:13 [PATCH] spi/pxa2xx: Restore private register bits Chew Chiau Ee
2013-11-28 11:22 ` Mark Brown [this message]
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