[PATCH v3 0/7] ARM: brcmstb: Add Broadcom STB SoC support

[PATCH v3 0/7] ARM: brcmstb: Add Broadcom STB SoC support

[Marc Carino]

This patchset contains the board support package for the
Broadcom BCM7445 ARM-based SoC [1]. These changes contain a
minimal set of code needed for a BCM7445-based board to boot
the Linux kernel.

These changes heavily leverage the OF/devicetree framework.

v3:
- rebased to v3.13-rc8
- switched to using 'multi_v7_defconfig'
- eliminated dependence on compile-time peripheral register access
- moved DT node iomap out from 'init_early'
- misc. minor cleanups from mailing-list discussion for v2

v2:
- rebased to v3.13-rc1
- moved implementation to 'mach-bcm' folder
- added CPU init for B15

v1:
- initial submission

[1] http://www.broadcom.com/products/Cable/Cable-Set-Top-Box-Solutions/BCM7445

Marc Carino (7):
  ARM: brcmstb: add infrastructure for ARM-based Broadcom STB SoCs
  ARM: brcmstb: add debug UART for earlyprintk support
  ARM: do CPU-specific init for Broadcom Brahma15 cores
  ARM: brcmstb: add CPU binding for Broadcom Brahma15
  ARM: brcmstb: add misc. DT bindings for brcm,brcmstb-*
  ARM: brcmstb: gic: add compatible string for Broadcom Brahma15
  ARM: brcmstb: dts: add a reference DTS for Broadcom 7445

 .../devicetree/bindings/arm/brcm-brcmstb.txt       |   43 ++++
 Documentation/devicetree/bindings/arm/cpus.txt     |    1 +
 Documentation/devicetree/bindings/arm/gic.txt      |    1 +
 arch/arm/Kconfig.debug                             |   16 ++-
 arch/arm/boot/dts/brcmstb-7445.dts                 |  104 ++++++++
 arch/arm/configs/multi_v7_defconfig                |    1 +
 arch/arm/mach-bcm/Kconfig                          |   14 +
 arch/arm/mach-bcm/Makefile                         |    4 +
 arch/arm/mach-bcm/brcmstb.c                        |  146 +++++++++++
 arch/arm/mach-bcm/brcmstb.h                        |   46 ++++
 arch/arm/mach-bcm/headsmp-brcmstb.S                |   34 +++
 arch/arm/mach-bcm/hotplug-brcmstb.c                |  252 ++++++++++++++++++++
 arch/arm/mm/proc-v7.S                              |   11 +
 13 files changed, 672 insertions(+), 1 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/brcm-brcmstb.txt
 create mode 100644 arch/arm/boot/dts/brcmstb-7445.dts
 create mode 100644 arch/arm/mach-bcm/brcmstb.c
 create mode 100644 arch/arm/mach-bcm/brcmstb.h
 create mode 100644 arch/arm/mach-bcm/headsmp-brcmstb.S
 create mode 100644 arch/arm/mach-bcm/hotplug-brcmstb.c

[PATCH v3 1/7] ARM: brcmstb: add infrastructure for ARM-based Broadcom STB SoCs

[Marc Carino]

The BCM7xxx series of Broadcom SoCs are used primarily in set-top boxes.

This patch adds machine support for the ARM-based Broadcom SoCs.

Signed-off-by: Marc Carino <marc.ceeeee@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
---
 arch/arm/configs/multi_v7_defconfig |    1 +
 arch/arm/mach-bcm/Kconfig           |   14 ++
 arch/arm/mach-bcm/Makefile          |    4 +
 arch/arm/mach-bcm/brcmstb.c         |  146 ++++++++++++++++++++
 arch/arm/mach-bcm/brcmstb.h         |   46 +++++++
 arch/arm/mach-bcm/headsmp-brcmstb.S |   34 +++++
 arch/arm/mach-bcm/hotplug-brcmstb.c |  252 +++++++++++++++++++++++++++++++++++
 7 files changed, 497 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-bcm/brcmstb.c
 create mode 100644 arch/arm/mach-bcm/brcmstb.h
 create mode 100644 arch/arm/mach-bcm/headsmp-brcmstb.S
 create mode 100644 arch/arm/mach-bcm/hotplug-brcmstb.c

diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index c1df4e9..7028d11 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -7,6 +7,7 @@ CONFIG_MACH_ARMADA_370=y
 CONFIG_MACH_ARMADA_XP=y
 CONFIG_ARCH_BCM=y
 CONFIG_ARCH_BCM_MOBILE=y
+CONFIG_ARCH_BRCMSTB=y
 CONFIG_GPIO_PCA953X=y
 CONFIG_ARCH_HIGHBANK=y
 CONFIG_ARCH_KEYSTONE=y
diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index 9fe6d88..2c1ae83 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -31,6 +31,20 @@ config ARCH_BCM_MOBILE
 	  BCM11130, BCM11140, BCM11351, BCM28145 and
 	  BCM28155 variants.
 
+config ARCH_BRCMSTB
+	bool "Broadcom BCM7XXX based boards" if ARCH_MULTI_V7
+	depends on MMU
+	select ARM_GIC
+	select MIGHT_HAVE_PCI
+	select HAVE_SMP
+	select HAVE_ARM_ARCH_TIMER
+	help
+	  Say Y if you intend to run the kernel on a Broadcom ARM-based STB
+	  chipset.
+
+	  This enables support for Broadcom ARM-based set-top box chipsets,
+	  including the 7445 family of chips.
+
 endmenu
 
 endif
diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
index c2ccd5a..b744a12 100644
--- a/arch/arm/mach-bcm/Makefile
+++ b/arch/arm/mach-bcm/Makefile
@@ -13,3 +13,7 @@
 obj-$(CONFIG_ARCH_BCM_MOBILE)	:= board_bcm281xx.o bcm_kona_smc.o bcm_kona_smc_asm.o kona.o
 plus_sec := $(call as-instr,.arch_extension sec,+sec)
 AFLAGS_bcm_kona_smc_asm.o	:=-Wa,-march=armv7-a$(plus_sec)
+
+obj-$(CONFIG_ARCH_BRCMSTB)	:= brcmstb.o
+obj-$(CONFIG_SMP)		+= headsmp-brcmstb.o
+obj-$(CONFIG_HOTPLUG_CPU)	+= hotplug-brcmstb.o
diff --git a/arch/arm/mach-bcm/brcmstb.c b/arch/arm/mach-bcm/brcmstb.c
new file mode 100644
index 0000000..eb9de26
--- /dev/null
+++ b/arch/arm/mach-bcm/brcmstb.c
@@ -0,0 +1,146 @@
+/*
+ * Copyright (C) 2013 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/console.h>
+#include <linux/clocksource.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/jiffies.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/printk.h>
+#include <linux/smp.h>
+
+#include <asm/cacheflush.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/time.h>
+
+#include "brcmstb.h"
+
+/***********************************************************************
+ * STB CPU (main application processor)
+ ***********************************************************************/
+
+static const char *brcmstb_match[] __initconst = {
+	"brcm,brcmstb-7445",
+	NULL
+};
+
+static void brcmstb_restart(enum reboot_mode mode, const char *cmd)
+{
+	struct device_node *np;
+	char *name;
+	void __iomem *rst_src_en;
+	void __iomem *sw_mstr_rst;
+
+	name = "brcm,brcmstb-gen-ctrl-v1";
+	np = of_find_compatible_node(NULL, NULL, name);
+	if (!np) {
+		pr_err("cannot find node %s\n", name);
+		return;
+	}
+
+	rst_src_en = of_iomap(np, GEN_CTRL_V1_RST_SRC_EN);
+	if (!rst_src_en) {
+		pr_err("can't iomap rst_src_en\n");
+		return;
+	}
+
+	sw_mstr_rst = of_iomap(np, GEN_CTRL_V1_SW_MSTR_RST);
+	if (!sw_mstr_rst) {
+		pr_err("can't iomap sw_mstr_rst\n");
+		return;
+	}
+
+	writel_relaxed(1, rst_src_en);
+	readl_relaxed(rst_src_en);
+
+	writel_relaxed(1, sw_mstr_rst);
+	readl_relaxed(sw_mstr_rst);
+
+	while (1)
+		;
+}
+
+static void __init brcmstb_init_early(void)
+{
+	add_preferred_console("ttyS", 0, "115200");
+}
+
+/***********************************************************************
+ * SMP boot
+ ***********************************************************************/
+
+#ifdef CONFIG_SMP
+static DEFINE_SPINLOCK(boot_lock);
+
+static void __cpuinit brcmstb_secondary_init(unsigned int cpu)
+{
+	/*
+	 * Synchronise with the boot thread.
+	 */
+	spin_lock(&boot_lock);
+	spin_unlock(&boot_lock);
+}
+
+static int __cpuinit brcmstb_boot_secondary(unsigned int cpu,
+					    struct task_struct *idle)
+{
+	/*
+	 * set synchronisation state between this boot processor
+	 * and the secondary one
+	 */
+	spin_lock(&boot_lock);
+
+	/* Bring up power to the core if necessary */
+	if (brcmstb_cpu_get_power_state(cpu) == 0)
+		brcmstb_cpu_power_on(cpu);
+
+	brcmstb_cpu_boot(cpu);
+
+	/*
+	 * now the secondary core is starting up let it run its
+	 * calibrations, then wait for it to finish
+	 */
+	spin_unlock(&boot_lock);
+
+	return 0;
+}
+
+struct smp_operations brcmstb_smp_ops __initdata = {
+	.smp_prepare_cpus	= brcmstb_cpu_ctrl_setup,
+	.smp_secondary_init	= brcmstb_secondary_init,
+	.smp_boot_secondary	= brcmstb_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+	.cpu_kill		= brcmstb_cpu_kill,
+	.cpu_die		= brcmstb_cpu_die,
+#endif
+};
+#endif
+
+DT_MACHINE_START(BRCMSTB, "Broadcom STB (Flattened Device Tree)")
+	.dt_compat	= brcmstb_match,
+	.restart	= brcmstb_restart,
+#ifdef CONFIG_SMP
+	.smp		= smp_ops(brcmstb_smp_ops),
+#endif
+	.init_early	= brcmstb_init_early,
+MACHINE_END
diff --git a/arch/arm/mach-bcm/brcmstb.h b/arch/arm/mach-bcm/brcmstb.h
new file mode 100644
index 0000000..9012afb
--- /dev/null
+++ b/arch/arm/mach-bcm/brcmstb.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2013 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __BRCMSTB_H__
+#define __BRCMSTB_H__
+
+#if !defined(__ASSEMBLY__)
+#include <linux/smp.h>
+#endif
+
+#if !defined(__ASSEMBLY__)
+extern void brcmstb_secondary_startup(void);
+extern void brcmstb_cpu_boot(unsigned int cpu);
+extern void brcmstb_cpu_power_on(unsigned int cpu);
+extern int brcmstb_cpu_get_power_state(unsigned int cpu);
+extern struct smp_operations brcmstb_smp_ops;
+#ifdef CONFIG_HOTPLUG_CPU
+extern void brcmstb_cpu_die(unsigned int cpu);
+extern int brcmstb_cpu_kill(unsigned int cpu);
+void __init brcmstb_cpu_ctrl_setup(unsigned int max_cpus);
+#else
+static inline void brcmstb_cpu_die(unsigned int cpu) {}
+static inline int brcmstb_cpu_kill(unsigned int cpu) {}
+static inline void __init brcmstb_cpu_ctrl_setup(unsigned int max_cpus) {}
+#endif
+#endif
+
+enum {
+	GEN_CTRL_V1_RST_SRC_EN = 0,
+	GEN_CTRL_V1_SW_MSTR_RST,
+	GEN_CTRL_V1_CPU_RST_CFG,
+	GEN_CTRL_V1_CPU_PWR_ZONE_CTRL,
+	GEN_CTRL_V1_STB_BOOT_HI_ADDR0,
+};
+
+#endif /* __BRCMSTB_H__ */
diff --git a/arch/arm/mach-bcm/headsmp-brcmstb.S b/arch/arm/mach-bcm/headsmp-brcmstb.S
new file mode 100644
index 0000000..57ec438
--- /dev/null
+++ b/arch/arm/mach-bcm/headsmp-brcmstb.S
@@ -0,0 +1,34 @@
+/*
+ * SMP boot code for secondary CPUs
+ * Based on arch/arm/mach-tegra/headsmp.S
+ *
+ * Copyright (C) 2010 NVIDIA, Inc.
+ * Copyright (C) 2013 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <asm/assembler.h>
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+        .section ".text.head", "ax"
+	__CPUINIT
+
+ENTRY(brcmstb_secondary_startup)
+        /*
+         * Ensure CPU is in a sane state by disabling all IRQs and switching
+         * into SVC mode.
+         */
+        setmode	PSR_I_BIT | PSR_F_BIT | SVC_MODE, r0
+
+        bl      v7_invalidate_l1
+        b       secondary_startup
+ENDPROC(brcmstb_secondary_startup)
diff --git a/arch/arm/mach-bcm/hotplug-brcmstb.c b/arch/arm/mach-bcm/hotplug-brcmstb.c
new file mode 100644
index 0000000..00de2ed
--- /dev/null
+++ b/arch/arm/mach-bcm/hotplug-brcmstb.c
@@ -0,0 +1,252 @@
+/*
+ * Broadcom STB CPU hotplug support for ARM
+ *
+ * Copyright (C) 2013 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/jiffies.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/printk.h>
+#include <linux/smp.h>
+
+#include <asm/cacheflush.h>
+#include <asm/mach-types.h>
+
+#include "brcmstb.h"
+
+enum {
+	ZONE_MAN_CLKEN_MASK		= BIT(0),
+	ZONE_MAN_RESET_CNTL_MASK	= BIT(1),
+	ZONE_MAN_MEM_PWR_MASK		= BIT(4),
+	ZONE_RESERVED_1_MASK		= BIT(5),
+	ZONE_MAN_ISO_CNTL_MASK		= BIT(6),
+	ZONE_MANUAL_CONTROL_MASK	= BIT(7),
+	ZONE_PWR_DN_REQ_MASK		= BIT(9),
+	ZONE_PWR_UP_REQ_MASK		= BIT(10),
+	ZONE_BLK_RST_ASSERT_MASK	= BIT(10),
+	ZONE_PWR_OFF_STATE_MASK		= BIT(26),
+	ZONE_PWR_ON_STATE_MASK		= BIT(26),
+	ZONE_DPG_PWR_STATE_MASK		= BIT(28),
+	ZONE_MEM_PWR_STATE_MASK		= BIT(29),
+	ZONE_RESET_STATE_MASK		= BIT(31),
+};
+
+static void __iomem *cpu_rst_cfg_reg;
+static void __iomem *cpu0_pwr_zone_ctrl_reg;
+static void __iomem *hif_cont_reg;
+
+DEFINE_PER_CPU(int, per_cpu_sw_state);
+
+static void __iomem *pwr_ctrl_get_base(unsigned int cpu)
+{
+	void __iomem *base = cpu0_pwr_zone_ctrl_reg;
+	base += (cpu * 4);
+	return base;
+}
+
+static u32 pwr_ctrl_rd(unsigned int cpu)
+{
+	void __iomem *base = pwr_ctrl_get_base(cpu);
+	return readl_relaxed(base);
+}
+
+static void pwr_ctrl_wr(unsigned int cpu, u32 val)
+{
+	void __iomem *base = pwr_ctrl_get_base(cpu);
+	writel(val, base);
+}
+
+void brcmstb_cpu_boot(unsigned int cpu)
+{
+	unsigned long boot_vector;
+	const int reg_ofs = cpu * 8;
+	u32 val;
+
+	pr_info("SMP: Booting CPU%d...\n", cpu);
+
+	/*
+	* set the reset vector to point to the secondary_startup
+	* routine
+	*/
+	boot_vector = virt_to_phys(brcmstb_secondary_startup);
+	writel_relaxed(0, hif_cont_reg + reg_ofs);
+	writel_relaxed(boot_vector, hif_cont_reg + 4 + reg_ofs);
+
+	flush_cache_all();
+
+	/* unhalt the cpu */
+	val = readl_relaxed(cpu_rst_cfg_reg);
+	val &= ~BIT(cpu);
+	writel_relaxed(val, cpu_rst_cfg_reg);
+}
+
+void brcmstb_cpu_power_on(unsigned int cpu)
+{
+	/*
+	 * The secondary cores power was cut, so we must go through
+	 * power-on initialization.
+	 */
+	u32 tmp;
+
+	pr_info("SMP: Powering up CPU%d...\n", cpu);
+
+	/* Request zone power up */
+	pwr_ctrl_wr(cpu, ZONE_PWR_UP_REQ_MASK);
+
+	/* Wait for the power up FSM to complete */
+	do {
+		tmp = pwr_ctrl_rd(cpu);
+	} while (!(tmp & ZONE_PWR_ON_STATE_MASK));
+
+	per_cpu(per_cpu_sw_state, cpu) = 1;
+}
+
+int brcmstb_cpu_get_power_state(unsigned int cpu)
+{
+	int tmp = pwr_ctrl_rd(cpu);
+	return (tmp & ZONE_RESET_STATE_MASK) ? 0 : 1;
+}
+
+void __ref brcmstb_cpu_die(unsigned int cpu)
+{
+	/* Derived from misc_bpcm_arm.c */
+
+	/* Clear SCTLR.C bit */
+	__asm__(
+		"mrc	p15, 0, r0, c1, c0, 0\n"
+		"bic	r0, r0, #(1 << 2)\n"
+		"mcr	p15, 0, r0, c1, c0, 0\n"
+		: /* no output */
+		: /* no input */
+		: "r0"	/* clobber r0 */
+	);
+
+	/*
+	 * Instruction barrier to ensure cache is really disabled before
+	 * cleaning/invalidating the caches
+	 */
+	isb();
+
+	flush_cache_all();
+
+	/* Invalidate all instruction caches to PoU (ICIALLU) */
+	/* Data sync. barrier to ensure caches have emptied out */
+	__asm__("mcr	p15, 0, r0, c7, c5, 0\n" : : : "r0");
+	dsb();
+
+	/*
+	 * Clear ACTLR.SMP bit to prevent broadcast TLB messages from reaching
+	 * this core
+	 */
+	__asm__(
+		"mrc	p15, 0, r0, c1, c0, 1\n"
+		"bic	r0, r0, #(1 << 6)\n"
+		"mcr	p15, 0, r0, c1, c0, 1\n"
+		: /* no output */
+		: /* no input */
+		: "r0"	/* clobber r0 */
+	);
+
+	/* Disable all IRQs for this CPU */
+	arch_local_irq_disable();
+
+	per_cpu(per_cpu_sw_state, cpu) = 0;
+
+	/*
+	 * Final full barrier to ensure everything before this instruction has
+	 * quiesced.
+	 */
+	isb();
+	dsb();
+
+	/* Sit and wait to die */
+	wfi();
+
+	/* We should never get here... */
+	nop();
+	panic("Spurious interrupt on CPU %d received!\n", cpu);
+}
+
+int brcmstb_cpu_kill(unsigned int cpu)
+{
+	u32 tmp;
+	u32 val;
+
+	pr_info("SMP: Powering down CPU%d...\n", cpu);
+
+	while (per_cpu(per_cpu_sw_state, cpu))
+		;
+
+	/* Program zone reset */
+	pwr_ctrl_wr(cpu, ZONE_RESET_STATE_MASK | ZONE_BLK_RST_ASSERT_MASK |
+			      ZONE_PWR_DN_REQ_MASK);
+
+	/* Verify zone reset */
+	tmp = pwr_ctrl_rd(cpu);
+	if (!(tmp & ZONE_RESET_STATE_MASK))
+		pr_err("%s: Zone reset bit for CPU %d not asserted!\n",
+			__func__, cpu);
+
+	/* Wait for power down */
+	do {
+		tmp = pwr_ctrl_rd(cpu);
+	} while (!(tmp & ZONE_PWR_OFF_STATE_MASK));
+
+	/* Settle-time from Broadcom-internal DVT reference code */
+	udelay(7);
+
+	/* Assert reset on the CPU */
+	val = readl_relaxed(cpu_rst_cfg_reg);
+	val |= BIT(cpu);
+	writel_relaxed(val, cpu_rst_cfg_reg);
+
+	return 1;
+}
+
+void __init brcmstb_cpu_ctrl_setup(unsigned int max_cpus)
+{
+	struct device_node *np;
+	char *name;
+
+	name = "brcm,brcmstb-gen-ctrl-v1";
+	np = of_find_compatible_node(NULL, NULL, name);
+	if (!np) {
+		pr_err("can't find compatible node %s\n", name);
+		return;
+	}
+
+	cpu_rst_cfg_reg = of_iomap(np, GEN_CTRL_V1_CPU_RST_CFG);
+	if (!cpu_rst_cfg_reg) {
+		pr_err("iomap failed for cpu_rst_cfg_reg\n");
+		return;
+	}
+
+	cpu0_pwr_zone_ctrl_reg = of_iomap(np, GEN_CTRL_V1_CPU_PWR_ZONE_CTRL);
+	if (!cpu0_pwr_zone_ctrl_reg) {
+		pr_err("iomap failed for cpu0_pwr_zone_ctrl_reg\n");
+		return;
+	}
+
+	hif_cont_reg = of_iomap(np, GEN_CTRL_V1_STB_BOOT_HI_ADDR0);
+	if (!hif_cont_reg) {
+		pr_err("iomap failed for hif_cont_reg\n");
+		return;
+	}
+}
+
-- 
1.7.1

[PATCH v3 2/7] ARM: brcmstb: add debug UART for earlyprintk support

[Marc Carino]

Add the UART definitions needed to support earlyprintk on brcmstb machines.

Signed-off-by: Marc Carino <marc.ceeeee@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
---
 arch/arm/Kconfig.debug |   16 +++++++++++++++-
 1 files changed, 15 insertions(+), 1 deletions(-)

diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 5765abf..266c699 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -94,6 +94,17 @@ choice
 		depends on ARCH_BCM2835
 		select DEBUG_UART_PL01X
 
+	config DEBUG_BRCMSTB_UART
+		bool "Use BRCMSTB UART for low-level debug"
+		depends on ARCH_BRCMSTB
+		select DEBUG_UART_8250
+		help
+		  Say Y here if you want the debug print routines to direct
+		  their output to the first serial port on these devices.
+
+		  If you have a Broadcom STB chip and would like early print
+		  messages to appear over the UART, select this option.
+
 	config DEBUG_CLPS711X_UART1
 		bool "Kernel low-level debugging messages via UART1"
 		depends on ARCH_CLPS711X
@@ -988,6 +999,7 @@ config DEBUG_UART_PHYS
 	default 0x20064000 if DEBUG_RK29_UART1 || DEBUG_RK3X_UART2
 	default 0x20068000 if DEBUG_RK29_UART2 || DEBUG_RK3X_UART3
 	default 0x20201000 if DEBUG_BCM2835
+	default 0xf0406b00 if DEBUG_BRCMSTB_UART
 	default 0x4000e400 if DEBUG_LL_UART_EFM32
 	default 0x40090000 if ARCH_LPC32XX
 	default 0x40100000 if DEBUG_PXA_UART1
@@ -1029,6 +1041,7 @@ config DEBUG_UART_VIRT
 	default 0xf0009000 if DEBUG_CNS3XXX
 	default 0xf01fb000 if DEBUG_NOMADIK_UART
 	default 0xf0201000 if DEBUG_BCM2835
+	default 0xfc406b00 if DEBUG_BRCMSTB_UART
 	default 0xf11f1000 if ARCH_VERSATILE
 	default 0xf1600000 if ARCH_INTEGRATOR
 	default 0xf1c28000 if DEBUG_SUNXI_UART0
@@ -1091,7 +1104,8 @@ config DEBUG_UART_8250_WORD
 	default y if DEBUG_PICOXCELL_UART || DEBUG_SOCFPGA_UART || \
 		ARCH_KEYSTONE || \
 		DEBUG_DAVINCI_DMx_UART0 || DEBUG_DAVINCI_DA8XX_UART1 || \
-		DEBUG_DAVINCI_DA8XX_UART2 || DEBUG_DAVINCI_TNETV107X_UART1
+		DEBUG_DAVINCI_DA8XX_UART2 || DEBUG_DAVINCI_TNETV107X_UART1 || \
+		DEBUG_BRCMSTB_UART
 
 config DEBUG_UART_8250_FLOW_CONTROL
 	bool "Enable flow control for 8250 UART"
-- 
1.7.1

[PATCH v3 3/7] ARM: do CPU-specific init for Broadcom Brahma15 cores

[Marc Carino]

Perform any CPU-specific initialization required on the
Broadcom Brahma-15 core.

Signed-off-by: Marc Carino <marc.ceeeee@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
---
 arch/arm/mm/proc-v7.S |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index bd17819..98ea423 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -193,6 +193,7 @@ __v7_cr7mp_setup:
 	b	1f
 __v7_ca7mp_setup:
 __v7_ca15mp_setup:
+__v7_b15mp_setup:
 	mov	r10, #0
 1:
 #ifdef CONFIG_SMP
@@ -494,6 +495,16 @@ __v7_ca15mp_proc_info:
 	.size	__v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
 
 	/*
+	 * Broadcom Corporation Brahma-B15 processor.
+	 */
+	.type	__v7_b15mp_proc_info, #object
+__v7_b15mp_proc_info:
+	.long	0x420f00f0
+	.long	0xff0ffff0
+	__v7_proc __v7_b15mp_setup, hwcaps = HWCAP_IDIV
+	.size	__v7_b15mp_proc_info, . - __v7_b15mp_proc_info
+
+	/*
 	 * Qualcomm Inc. Krait processors.
 	 */
 	.type	__krait_proc_info, #object
-- 
1.7.1

[PATCH v3 4/7] ARM: brcmstb: add CPU binding for Broadcom Brahma15

[Marc Carino]

Add the Broadcom Brahma B15 CPU to the DT CPU binding list.

Signed-off-by: Marc Carino <marc.ceeeee@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
---
 Documentation/devicetree/bindings/arm/cpus.txt |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index 9130435..423b879 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -163,6 +163,7 @@ nodes to be present and contain the properties described below.
 			    "arm,cortex-r4"
 			    "arm,cortex-r5"
 			    "arm,cortex-r7"
+			    "brcm,brahma15"
 			    "faraday,fa526"
 			    "intel,sa110"
 			    "intel,sa1100"
-- 
1.7.1

[PATCH v3 5/7] ARM: brcmstb: add misc. DT bindings for brcm,brcmstb-*

[Marc Carino]

Document the bindings that the Broadcom STB platform needs
for proper bootup.

Signed-off-by: Marc Carino <marc.ceeeee@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
---
 .../devicetree/bindings/arm/brcm-brcmstb.txt       |   43 ++++++++++++++++++++
 1 files changed, 43 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/brcm-brcmstb.txt

diff --git a/Documentation/devicetree/bindings/arm/brcm-brcmstb.txt b/Documentation/devicetree/bindings/arm/brcm-brcmstb.txt
new file mode 100644
index 0000000..5f1aba7
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/brcm-brcmstb.txt
@@ -0,0 +1,43 @@
+Broadcom STB platforms Device Tree Bindings
+-------------------------------------------
+Boards with Broadcom Brahma15 ARM-based BCM7xxx SoC shall have the following
+properties.
+
+Required root node properties:
+
+    - compatible = "brcm,brcmstb-<chip_id>";
+
+Further, a node with the following compatible string shall be defined:
+
+    - compatible: "brcm,brcmstb-gen-ctrl-v1"
+
+brcmstb-gen-ctrl
+----------------
+This node describes the registers needed for reset and CPU power control.
+
+    - compatible: "brcm,brcmstb-gen-ctrl-v1"
+    - properties:
+        o reg = <rst-src-en-reg-base len
+                 sw-mstr-rst-reg-base len
+                 cpu-rst-cfg-reg-base len
+                 cpu-pwr-zone-ctrl-reg-base len
+                 stb-boot-hi-addr0-reg len>;
+
+example:
+/ {
+    model = "Broadcom STB";
+    compatible =  "brcm,brcmstb-7445";
+
+    /* snip */
+
+    gen-ctrl {
+        compatible = "brcm,brcmstb-gen-ctrl-v1";
+        reg = <0xf0404304 0x4
+               0xf0404308 0x4
+               0xf03e2578 0x4
+               0xf03e2488 0x10
+               0xf0452000 0x20>;
+    };
+
+    /* snip */
+};
-- 
1.7.1

[PATCH v3 6/7] ARM: brcmstb: gic: add compatible string for Broadcom Brahma15

[Marc Carino]

Document the Broadcom Brahma B15 GIC implementation as compatible
with the ARM GIC standard.

Signed-off-by: Marc Carino <marc.ceeeee@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
---
 Documentation/devicetree/bindings/arm/gic.txt |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/gic.txt b/Documentation/devicetree/bindings/arm/gic.txt
index 3dfb0c0..b7d7970 100644
--- a/Documentation/devicetree/bindings/arm/gic.txt
+++ b/Documentation/devicetree/bindings/arm/gic.txt
@@ -15,6 +15,7 @@ Main node required properties:
 	"arm,cortex-a9-gic"
 	"arm,cortex-a7-gic"
 	"arm,arm11mp-gic"
+	"brcm,brahma15-gic"
 - interrupt-controller : Identifies the node as an interrupt controller
 - #interrupt-cells : Specifies the number of cells needed to encode an
   interrupt source.  The type shall be a <u32> and the value shall be 3.
-- 
1.7.1

[PATCH v3 7/7] ARM: brcmstb: dts: add a reference DTS for Broadcom 7445

[Marc Carino]

Add a sample DTS which will allow bootup of a board populated
with the BCM7445 chip.

Signed-off-by: Marc Carino <marc.ceeeee@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
---
 arch/arm/boot/dts/brcmstb-7445.dts |  104 ++++++++++++++++++++++++++++++++++++
 1 files changed, 104 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/boot/dts/brcmstb-7445.dts

diff --git a/arch/arm/boot/dts/brcmstb-7445.dts b/arch/arm/boot/dts/brcmstb-7445.dts
new file mode 100644
index 0000000..cbe73b4
--- /dev/null
+++ b/arch/arm/boot/dts/brcmstb-7445.dts
@@ -0,0 +1,104 @@
+/dts-v1/;
+/include/ "skeleton.dtsi"
+
+/ {
+	#address-cells = <0x1>;
+	#size-cells = <0x1>;
+	model = "Broadcom STB (7445)";
+	compatible = "brcm,brcmstb-7445";
+	interrupt-parent = <&gic>;
+
+	chosen {};
+
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x40000000 0x40000000 0x40000000 0x80000000 0x40000000>;
+	};
+
+	cpupll: cpupll@0 {
+		#clock-cells = <0x0>;
+		compatible = "fixed-clock";
+		clock-frequency = <1500000000>;
+	};
+
+	cpuclk: cpu-clk-div@0 {
+		#clock-cells = <0x0>;
+		compatible = "brcm,brcmstb-cpu-clk-div";
+		reg = <0xf03e257c 0x4>;
+		clocks = <&cpupll>;
+		div-table = <0x0 0x1 0x11 0x2 0x12 0x4 0x13 0x8 0x14 0x10>;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			compatible = "brcm,brahma15";
+			operating-points = <0x16e360 0x0
+					    0x0b71b0 0x0
+					    0x05b8d8 0x0
+					    0x02dc6c 0x0
+					    0x016e36 0x0>;
+			clocks = <&cpuclk>;
+			device_type = "cpu";
+			reg = <0>;
+			clock-frequency = <1500000000>;
+		};
+
+		cpu@1 {
+			compatible = "brcm,brahma15";
+			device_type = "cpu";
+			reg = <1>;
+			clock-frequency = <1500000000>;
+		};
+
+		cpu@2 {
+			compatible = "brcm,brahma15";
+			device_type = "cpu";
+			reg = <2>;
+			clock-frequency = <1500000000>;
+		};
+
+		cpu@3 {
+			compatible = "brcm,brahma15";
+			device_type = "cpu";
+			reg = <3>;
+			clock-frequency = <1500000000>;
+		};
+	};
+
+	gic: interrupt-controller@ffd00000 {
+		compatible = "brcm,brahma15-gic", "arm,cortex-a15-gic";
+		reg = <0xffd01000 0x1000
+		       0xffd02000 0x2000>;
+		interrupt-controller;
+		#interrupt-cells = <0x3>;
+	};
+
+	timer {
+		compatible = "arm,armv7-timer";
+		interrupts = <1 13 0xf08
+			      1 14 0xf08
+			      1 11 0xf08
+			      1 10 0xf08>;
+	};
+
+	serial@f0406b00 {
+		compatible = "ns16550a";
+		reg = <0xf0406b00 0x20>;
+		reg-shift = <0x2>;
+		reg-io-width = <0x4>;
+		interrupts = <0x0 0x4b 0x4>;
+		clock-frequency = <0x4d3f640>;
+	};
+
+	gen-ctrl {
+		compatible = "brcm,brcmstb-gen-ctrl-v1";
+		reg = <0xf0404304 0x4
+		       0xf0404308 0x4
+		       0xf03e2578 0x4
+		       0xf03e2488 0x10
+		       0xf0452000 0x20>;
+	};
+};
-- 
1.7.1

Re: [PATCH v3 7/7] ARM: brcmstb: dts: add a reference DTS for Broadcom 7445

[Arnd Bergmann]

On Wednesday 15 January 2014, Marc Carino wrote:
> +       gen-ctrl {
> +               compatible = "brcm,brcmstb-gen-ctrl-v1";
> +               reg = <0xf0404304 0x4
> +                      0xf0404308 0x4
> +                      0xf03e2578 0x4
> +                      0xf03e2488 0x10
> +                      0xf0452000 0x20>;
> +       };

Sorry I didn't get back to you on this when we discussed the previous
version. I'm actually less happy with this DT representation than the
original. What I take from your description is that you have multiple
register ranges that basically combine more-or-less random registers
that belong into different Linux subsystems.

I think the best way to deal with this is to have the "syscon" driver
handle the multiplexing between the various drivers that need access
to the registers. It would look something like (taking the numbers
from your previous patch):

	ahb {
		ranges = <0 0xf0000000 0x1000000>; /* 16 MB remapped registers */

		hif-cpubuictrl: syscon@3e2400 {
			compatible = "brcm,7445-cpubioctrl", "syscon";
			reg = <0x3e2000, 0x1000>;
		};

		hif-continuation: syscon@45200 {
			compatible = "brcm,7445-hif-continuation", "syscon";
			reg = <0x452000, 0x1000>;
		};

		sun-top-ctrl: ...
	};

This lets the syscon driver find and map the three register areas.
Drivers that need access to the registers then do 

	reset {
		compatible = "brcm,7445-reset-ctrl";
		syscon = <&sun-top-ctrl 0x300 0x100>;
		#reset-cells = <1>;
	};

And then you can add a regular device driver to drivers/reset that provides
a device_reset() API to other drivers, or a system-reset function to be
registered as arm_pm_restart. This driver would use
syscon_regmap_lookup_by_phandle() to get access to a regmap pointer,
and then use either hardcoded offsets into the regmap, or get those
offsets from numbers in the devicetree, as provided in the example
above.

	Arnd

Re: [PATCH v3 4/7] ARM: brcmstb: add CPU binding for Broadcom Brahma15

[Mark Rutland]

On Tue, Jan 14, 2014 at 11:48:50PM +0000, Marc Carino wrote:
> Add the Broadcom Brahma B15 CPU to the DT CPU binding list.
> 
> Signed-off-by: Marc Carino <marc.ceeeee@gmail.com>
> Acked-by: Florian Fainelli <f.fainelli@gmail.com>
> ---
>  Documentation/devicetree/bindings/arm/cpus.txt |    1 +
>  1 files changed, 1 insertions(+), 0 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
> index 9130435..423b879 100644
> --- a/Documentation/devicetree/bindings/arm/cpus.txt
> +++ b/Documentation/devicetree/bindings/arm/cpus.txt
> @@ -163,6 +163,7 @@ nodes to be present and contain the properties described below.
>  			    "arm,cortex-r4"
>  			    "arm,cortex-r5"
>  			    "arm,cortex-r7"
> +			    "brcm,brahma15"

Given all the documentation I can find online calls the CPU
"Brahma-B15", would it not make more sense for this to be
"brcm,brahma-b15"? 

That would match what we do for the ARM Cortex-[ar]\d processors.

Otherwise, this looks fine to me.

Cheers,
Mark.

Re: [PATCH v3 5/7] ARM: brcmstb: add misc. DT bindings for brcm,brcmstb-*

[Mark Rutland]

On Tue, Jan 14, 2014 at 11:48:51PM +0000, Marc Carino wrote:
> Document the bindings that the Broadcom STB platform needs
> for proper bootup.
> 
> Signed-off-by: Marc Carino <marc.ceeeee@gmail.com>
> Acked-by: Florian Fainelli <f.fainelli@gmail.com>
> ---
>  .../devicetree/bindings/arm/brcm-brcmstb.txt       |   43 ++++++++++++++++++++
>  1 files changed, 43 insertions(+), 0 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/arm/brcm-brcmstb.txt
> 
> diff --git a/Documentation/devicetree/bindings/arm/brcm-brcmstb.txt b/Documentation/devicetree/bindings/arm/brcm-brcmstb.txt
> new file mode 100644
> index 0000000..5f1aba7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/brcm-brcmstb.txt
> @@ -0,0 +1,43 @@
> +Broadcom STB platforms Device Tree Bindings
> +-------------------------------------------
> +Boards with Broadcom Brahma15 ARM-based BCM7xxx SoC shall have the following
> +properties.
> +
> +Required root node properties:
> +
> +    - compatible = "brcm,brcmstb-<chip_id>";

I'd prefer it if variants were listed explicitly (as it makes it far
easier to grep for). Something like:

- compatible: should contain one of:
  * "brcm,brcmsrb-7445"
  * "brcm,brcmsrb-7446"

> +
> +Further, a node with the following compatible string shall be defined:
> +
> +    - compatible: "brcm,brcmstb-gen-ctrl-v1"

It's probably better to say a brcmstb-gen-ctrl node (described below)
should be present, or you'll have two places to update the compatible
strings for each new variant...

> +
> +brcmstb-gen-ctrl
> +----------------
> +This node describes the registers needed for reset and CPU power control.
> +
> +    - compatible: "brcm,brcmstb-gen-ctrl-v1"
> +    - properties:

This looks odd, compatible is itself a property.

> +        o reg = <rst-src-en-reg-base len
> +                 sw-mstr-rst-reg-base len
> +                 cpu-rst-cfg-reg-base len
> +                 cpu-pwr-zone-ctrl-reg-base len
> +                 stb-boot-hi-addr0-reg len>;

This would be nicer as something like follows, but with less
abberviation (unless these names are from a datasheet for the hardware).

- reg: a list of base-address size pairs:
  * The first entry should cover the sw-mstr-rst registers
  * The second entry should cover the cpu-rst-cfg registers
  * The third entry should cover the cpu-pwr-zone registers
  * The fourth entry should cover the stb-boot-hi-addr0 registers

It may make sense to use reg-names, future revisions might change
things.

> +
> +example:
> +/ {
> +    model = "Broadcom STB";
> +    compatible =  "brcm,brcmstb-7445";
> +
> +    /* snip */
> +
> +    gen-ctrl {
> +        compatible = "brcm,brcmstb-gen-ctrl-v1";
> +        reg = <0xf0404304 0x4
> +               0xf0404308 0x4
> +               0xf03e2578 0x4
> +               0xf03e2488 0x10
> +               0xf0452000 0x20>;

Nit: please bracket each entry individually:

reg = <0xf0404304 0x4>,
      <0xf0404308 0x4>,
      <0xf03e2578 0x4>,
      <0xf03e2488 0x10>,
      <0xf0452000 0x20>;

Also, these look to be single registers in a larger register bank. Is
there any reason you can't describe the bank(s) they are in? That'll
give you more flexibility in the driver...

Thanks,
Mark

Re: [PATCH v3 5/7] ARM: brcmstb: add misc. DT bindings for brcm,brcmstb-*

[Arnd Bergmann]

On Wednesday 15 January 2014 17:11:55 Mark Rutland wrote:
> > +
> > +Further, a node with the following compatible string shall be defined:
> > +
> > +    - compatible: "brcm,brcmstb-gen-ctrl-v1"
> 
> It's probably better to say a brcmstb-gen-ctrl node (described below)
> should be present, or you'll have two places to update the compatible
> strings for each new variant...

See my other reply on this node. The previous patch version had a different
approach to these registers, and I suggested doing yet another one and
using syscon.

	Arnd

Re: [PATCH v3 3/7] ARM: do CPU-specific init for Broadcom Brahma15 cores

[Will Deacon]

On Tue, Jan 14, 2014 at 11:48:49PM +0000, Marc Carino wrote:
> Perform any CPU-specific initialization required on the
> Broadcom Brahma-15 core.
> 
> Signed-off-by: Marc Carino <marc.ceeeee@gmail.com>
> Acked-by: Florian Fainelli <f.fainelli@gmail.com>
> ---
>  arch/arm/mm/proc-v7.S |   11 +++++++++++
>  1 files changed, 11 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
> index bd17819..98ea423 100644
> --- a/arch/arm/mm/proc-v7.S
> +++ b/arch/arm/mm/proc-v7.S
> @@ -193,6 +193,7 @@ __v7_cr7mp_setup:
>  	b	1f
>  __v7_ca7mp_setup:
>  __v7_ca15mp_setup:
> +__v7_b15mp_setup:
>  	mov	r10, #0
>  1:
>  #ifdef CONFIG_SMP
> @@ -494,6 +495,16 @@ __v7_ca15mp_proc_info:
>  	.size	__v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
>  
>  	/*
> +	 * Broadcom Corporation Brahma-B15 processor.
> +	 */
> +	.type	__v7_b15mp_proc_info, #object
> +__v7_b15mp_proc_info:
> +	.long	0x420f00f0
> +	.long	0xff0ffff0
> +	__v7_proc __v7_b15mp_setup, hwcaps = HWCAP_IDIV

You only need to specify HWCAP_IDIV if you screwed up your idregs (namely
CPUID_EXT_ISAR0). Do you actually need this for your core?

Will

Re: [PATCH v3 6/7] ARM: brcmstb: gic: add compatible string for Broadcom Brahma15

[Mark Rutland]

On Tue, Jan 14, 2014 at 11:48:52PM +0000, Marc Carino wrote:
> Document the Broadcom Brahma B15 GIC implementation as compatible
> with the ARM GIC standard.
> 
> Signed-off-by: Marc Carino <marc.ceeeee@gmail.com>
> Acked-by: Florian Fainelli <f.fainelli@gmail.com>
> ---
>  Documentation/devicetree/bindings/arm/gic.txt |    1 +
>  1 files changed, 1 insertions(+), 0 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/arm/gic.txt b/Documentation/devicetree/bindings/arm/gic.txt
> index 3dfb0c0..b7d7970 100644
> --- a/Documentation/devicetree/bindings/arm/gic.txt
> +++ b/Documentation/devicetree/bindings/arm/gic.txt
> @@ -15,6 +15,7 @@ Main node required properties:
>  	"arm,cortex-a9-gic"
>  	"arm,cortex-a7-gic"
>  	"arm,arm11mp-gic"
> +	"brcm,brahma15-gic"

Similarly to the cpu binding patch, I think this should be
"brcm,brahma-b15-gic".

It doesn't have to be done here, but it might make sense to add
"arm,gic-v2" for arbitrary GICv2 implementations to use as a fallback
compatible string.

Cheers,
Mark.

Re: [PATCH v3 7/7] ARM: brcmstb: dts: add a reference DTS for Broadcom 7445

[Mark Rutland]

On Tue, Jan 14, 2014 at 11:48:53PM +0000, Marc Carino wrote:
> Add a sample DTS which will allow bootup of a board populated
> with the BCM7445 chip.
> 
> Signed-off-by: Marc Carino <marc.ceeeee@gmail.com>
> Acked-by: Florian Fainelli <f.fainelli@gmail.com>
> ---
>  arch/arm/boot/dts/brcmstb-7445.dts |  104 ++++++++++++++++++++++++++++++++++++
>  1 files changed, 104 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/boot/dts/brcmstb-7445.dts
> 
> diff --git a/arch/arm/boot/dts/brcmstb-7445.dts b/arch/arm/boot/dts/brcmstb-7445.dts
> new file mode 100644
> index 0000000..cbe73b4
> --- /dev/null
> +++ b/arch/arm/boot/dts/brcmstb-7445.dts
> @@ -0,0 +1,104 @@
> +/dts-v1/;
> +/include/ "skeleton.dtsi"
> +
> +/ {
> +	#address-cells = <0x1>;
> +	#size-cells = <0x1>;

I see that there are some Xen patches floating around for the B15, so
presumably you have LPAE (and therefore can have physical addresses
wider than 32-bits).

Are all peripherals and memory in the bottom 4GB of the physical address
space? If not, I'd recommend you bump #address-cells (and #size-cells)
to <2> now, or you'll need to rewrite half the DT to add currently
missing peripherals...

Also, unless you're writing an address or mask it's usually nicer to
have the value in decimal rather than hex. Please could you get rid of
the 0x prefix on the #address-cells, #size-cells, #clock-cells values?

It's a minor issue, but it's nicer for humans to read...

> +	model = "Broadcom STB (7445)";
> +	compatible = "brcm,brcmstb-7445";
> +	interrupt-parent = <&gic>;
> +
> +	chosen {};
> +
> +	memory {
> +		device_type = "memory";
> +		reg = <0x0 0x40000000 0x40000000 0x40000000 0x80000000 0x40000000>;
> +	};

As a general note, where you have list properties, please bracket
elements individually (here and elsewhere) so it's possible to read,
e.g:

	reg = <0x00000000 0x40000000>,
	      <0x40000000 0x40000000>,
	      <0x80000000 0x40000000>;

In this case, the memory is contiguous, so you can describe it with one
reg entry:

	reg = <0x0 0xc0000000>;

> +
> +	cpupll: cpupll@0 {
> +		#clock-cells = <0x0>;
> +		compatible = "fixed-clock";
> +		clock-frequency = <1500000000>;
> +	};

The unit-address (the "@0") should go, as this doesn't have a reg entry.
same for the cpu-clk-div@0 node below:

> +
> +	cpuclk: cpu-clk-div@0 {
> +		#clock-cells = <0x0>;
> +		compatible = "brcm,brcmstb-cpu-clk-div";
> +		reg = <0xf03e257c 0x4>;
> +		clocks = <&cpupll>;
> +		div-table = <0x0 0x1 0x11 0x2 0x12 0x4 0x13 0x8 0x14 0x10>;
> +	};

The unit-address here should be f03e257c (or 0,f03e257c if you move to
#address-cells = <2>).

Is this binding documented anywhere? It doesn't seem to be added in this
series, and grep on mainline gave me nothing...

> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu@0 {
> +			compatible = "brcm,brahma15";

I think this string should change, as mentioned in my cpu binding
patch comments.

> +			operating-points = <0x16e360 0x0
> +					    0x0b71b0 0x0
> +					    0x05b8d8 0x0
> +					    0x02dc6c 0x0
> +					    0x016e36 0x0>;

These might be easier to read in decimal...

> +			clocks = <&cpuclk>;
> +			device_type = "cpu";
> +			reg = <0>;
> +			clock-frequency = <1500000000>;
> +		};
> +
> +		cpu@1 {
> +			compatible = "brcm,brahma15";
> +			device_type = "cpu";
> +			reg = <1>;
> +			clock-frequency = <1500000000>;
> +		};
> +
> +		cpu@2 {
> +			compatible = "brcm,brahma15";
> +			device_type = "cpu";
> +			reg = <2>;
> +			clock-frequency = <1500000000>;
> +		};
> +
> +		cpu@3 {
> +			compatible = "brcm,brahma15";
> +			device_type = "cpu";
> +			reg = <3>;
> +			clock-frequency = <1500000000>;
> +		};
> +	};
> +
> +	gic: interrupt-controller@ffd00000 {
> +		compatible = "brcm,brahma15-gic", "arm,cortex-a15-gic";
> +		reg = <0xffd01000 0x1000
> +		       0xffd02000 0x2000>;

I see you have Xen patches, and therefore presumably have a GIC with
virtualization features. Could you add the missing reg entries for the
virtual control and virtual cpu interface registers please?

Cheers,
Mark.

Re: [PATCH v3 5/7] ARM: brcmstb: add misc. DT bindings for brcm,brcmstb-*

[Florian Fainelli]

2014/1/15 Mark Rutland <mark.rutland@arm.com>:
> On Tue, Jan 14, 2014 at 11:48:51PM +0000, Marc Carino wrote:
>> Document the bindings that the Broadcom STB platform needs
>> for proper bootup.
>>
>> Signed-off-by: Marc Carino <marc.ceeeee@gmail.com>
>> Acked-by: Florian Fainelli <f.fainelli@gmail.com>
>> ---
>>  .../devicetree/bindings/arm/brcm-brcmstb.txt       |   43 ++++++++++++++++++++
>>  1 files changed, 43 insertions(+), 0 deletions(-)
>>  create mode 100644 Documentation/devicetree/bindings/arm/brcm-brcmstb.txt
>>
>> diff --git a/Documentation/devicetree/bindings/arm/brcm-brcmstb.txt b/Documentation/devicetree/bindings/arm/brcm-brcmstb.txt
>> new file mode 100644
>> index 0000000..5f1aba7
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/brcm-brcmstb.txt
>> @@ -0,0 +1,43 @@
>> +Broadcom STB platforms Device Tree Bindings
>> +-------------------------------------------
>> +Boards with Broadcom Brahma15 ARM-based BCM7xxx SoC shall have the following
>> +properties.
>> +
>> +Required root node properties:
>> +
>> +    - compatible = "brcm,brcmstb-<chip_id>";
>
> I'd prefer it if variants were listed explicitly (as it makes it far
> easier to grep for). Something like:
>
> - compatible: should contain one of:
>   * "brcm,brcmsrb-7445"
>   * "brcm,brcmsrb-7446"

For consistency with other Broadcom SoCs in mainline, as well as
making it easier to grep for products, I would be inclined to use:

compatible = "brcm,bcm7445", with the fallback compatible string "brcm,brcmstb".
-- 
Florian

Re: [PATCH v3 7/7] ARM: brcmstb: dts: add a reference DTS for Broadcom 7445

[Marc]

Hi Arnd,

Thank you for the suggestion - it's exactly what we were looking for!

Regards,
Marc

Sent from my phone

> On Jan 15, 2014, at 5:10 AM, Arnd Bergmann <arnd@arndb.de> wrote:
> 
>> On Wednesday 15 January 2014, Marc Carino wrote:
>> +       gen-ctrl {
>> +               compatible = "brcm,brcmstb-gen-ctrl-v1";
>> +               reg = <0xf0404304 0x4
>> +                      0xf0404308 0x4
>> +                      0xf03e2578 0x4
>> +                      0xf03e2488 0x10
>> +                      0xf0452000 0x20>;
>> +       };
> 
> Sorry I didn't get back to you on this when we discussed the previous
> version. I'm actually less happy with this DT representation than the
> original. What I take from your description is that you have multiple
> register ranges that basically combine more-or-less random registers
> that belong into different Linux subsystems.
> 
> I think the best way to deal with this is to have the "syscon" driver
> handle the multiplexing between the various drivers that need access
> to the registers. It would look something like (taking the numbers
> from your previous patch):
> 
>    ahb {
>        ranges = <0 0xf0000000 0x1000000>; /* 16 MB remapped registers */
> 
>        hif-cpubuictrl: syscon@3e2400 {
>            compatible = "brcm,7445-cpubioctrl", "syscon";
>            reg = <0x3e2000, 0x1000>;
>        };
> 
>        hif-continuation: syscon@45200 {
>            compatible = "brcm,7445-hif-continuation", "syscon";
>            reg = <0x452000, 0x1000>;
>        };
> 
>        sun-top-ctrl: ...
>    };
> 
> This lets the syscon driver find and map the three register areas.
> Drivers that need access to the registers then do 
> 
>    reset {
>        compatible = "brcm,7445-reset-ctrl";
>        syscon = <&sun-top-ctrl 0x300 0x100>;
>        #reset-cells = <1>;
>    };
> 
> And then you can add a regular device driver to drivers/reset that provides
> a device_reset() API to other drivers, or a system-reset function to be
> registered as arm_pm_restart. This driver would use
> syscon_regmap_lookup_by_phandle() to get access to a regmap pointer,
> and then use either hardcoded offsets into the regmap, or get those
> offsets from numbers in the devicetree, as provided in the example
> above.
> 
>    Arnd

Re: [PATCH v3 7/7] ARM: brcmstb: dts: add a reference DTS for Broadcom 7445

[Marc C]

Hello Arnd,

> And then you can add a regular device driver to drivers/reset that provides a
> device_reset() API to other drivers, or a system-reset function to be registered as
> arm_pm_restart. This driver would use syscon_regmap_lookup_by_phandle() to get access
> to a regmap pointer, and then use either hardcoded offsets into the regmap, or get
> those offsets from numbers in the devicetree, as provided in the example above.

I was able to port a standalone "reboot" driver using syscon + regmap. However, for the
SMP initialization case, it turns out that syscon is configured *after* SMP init. Do you
have any advice for this type of situation?

I'd hate to go around in circles, but without resorting to hard-coded offsets, perhaps I
can just add the remaining "non-regmap" register offsets in the DT?

Thanks,
Marc

On 01/15/2014 10:22 AM, Marc wrote:
> Hi Arnd,
> 
> Thank you for the suggestion - it's exactly what we were looking for!
> 
> Regards,
> Marc
> 
> Sent from my phone
> 
>> On Jan 15, 2014, at 5:10 AM, Arnd Bergmann <arnd@arndb.de> wrote:
>>
>>> On Wednesday 15 January 2014, Marc Carino wrote:
>>> +       gen-ctrl {
>>> +               compatible = "brcm,brcmstb-gen-ctrl-v1";
>>> +               reg = <0xf0404304 0x4
>>> +                      0xf0404308 0x4
>>> +                      0xf03e2578 0x4
>>> +                      0xf03e2488 0x10
>>> +                      0xf0452000 0x20>;
>>> +       };
>>
>> Sorry I didn't get back to you on this when we discussed the previous
>> version. I'm actually less happy with this DT representation than the
>> original. What I take from your description is that you have multiple
>> register ranges that basically combine more-or-less random registers
>> that belong into different Linux subsystems.
>>
>> I think the best way to deal with this is to have the "syscon" driver
>> handle the multiplexing between the various drivers that need access
>> to the registers. It would look something like (taking the numbers
>> from your previous patch):
>>
>>    ahb {
>>        ranges = <0 0xf0000000 0x1000000>; /* 16 MB remapped registers */
>>
>>        hif-cpubuictrl: syscon@3e2400 {
>>            compatible = "brcm,7445-cpubioctrl", "syscon";
>>            reg = <0x3e2000, 0x1000>;
>>        };
>>
>>        hif-continuation: syscon@45200 {
>>            compatible = "brcm,7445-hif-continuation", "syscon";
>>            reg = <0x452000, 0x1000>;
>>        };
>>
>>        sun-top-ctrl: ...
>>    };
>>
>> This lets the syscon driver find and map the three register areas.
>> Drivers that need access to the registers then do 
>>
>>    reset {
>>        compatible = "brcm,7445-reset-ctrl";
>>        syscon = <&sun-top-ctrl 0x300 0x100>;
>>        #reset-cells = <1>;
>>    };
>>
>> And then you can add a regular device driver to drivers/reset that provides
>> a device_reset() API to other drivers, or a system-reset function to be
>> registered as arm_pm_restart. This driver would use
>> syscon_regmap_lookup_by_phandle() to get access to a regmap pointer,
>> and then use either hardcoded offsets into the regmap, or get those
>> offsets from numbers in the devicetree, as provided in the example
>> above.
>>
>>    Arnd

Re: [PATCH v3 7/7] ARM: brcmstb: dts: add a reference DTS for Broadcom 7445

[Arnd Bergmann]

On Thursday 16 January 2014, Marc C wrote:
> > And then you can add a regular device driver to drivers/reset that provides a
> > device_reset() API to other drivers, or a system-reset function to be registered as
> > arm_pm_restart. This driver would use syscon_regmap_lookup_by_phandle() to get access
> > to a regmap pointer, and then use either hardcoded offsets into the regmap, or get
> > those offsets from numbers in the devicetree, as provided in the example above.
> 
> I was able to port a standalone "reboot" driver using syscon + regmap. However, for the
> SMP initialization case, it turns out that syscon is configured after SMP init. Do you
> have any advice for this type of situation?
> 
> I'd hate to go around in circles, but without resorting to hard-coded offsets, perhaps I
> can just add the remaining "non-regmap" register offsets in the DT?

You are not the first one to stumble over this problem. There are
two ways to get out of it, and we should probably implement both in
the long run:

1. Other platforms also require the syscon driver to be active before
the regular device driver probing starts. Michal Simek has the same
issue in the zynq clock driver that you have for SMP initialization.
We have talked about this with Mark Brown already, and I think we will
find a solution for this in the end, but it's not as straightforward
as I first hoped. We can probably use help in this area.

2. There is actually no reason for the SMP code to be called this early,
and multiple platforms would like to move SMP init to a later stage.
Stephen Boyd has recently started reworking the way we do SMP init,
and he may have some more insight.

In the meantime, I'd suggest you do the binding under the assumption
that it will work eventually, and then work around the current limitations
in the SMP code by looking for the device nodes you need and map them
manually, as you did in the previous versions of your patch set.

	Arnd

Re: [PATCH v3 7/7] ARM: brcmstb: dts: add a reference DTS for Broadcom 7445

[Michal Simek]

On 01/16/2014 12:19 PM, Arnd Bergmann wrote:
> On Thursday 16 January 2014, Marc C wrote:
>>> And then you can add a regular device driver to drivers/reset that provides a
>>> device_reset() API to other drivers, or a system-reset function to be registered as
>>> arm_pm_restart. This driver would use syscon_regmap_lookup_by_phandle() to get access
>>> to a regmap pointer, and then use either hardcoded offsets into the regmap, or get
>>> those offsets from numbers in the devicetree, as provided in the example above.
>>
>> I was able to port a standalone "reboot" driver using syscon + regmap. However, for the
>> SMP initialization case, it turns out that syscon is configured after SMP init. Do you
>> have any advice for this type of situation?
>>
>> I'd hate to go around in circles, but without resorting to hard-coded offsets, perhaps I
>> can just add the remaining "non-regmap" register offsets in the DT?
> 
> You are not the first one to stumble over this problem. There are
> two ways to get out of it, and we should probably implement both in
> the long run:
> 
> 1. Other platforms also require the syscon driver to be active before
> the regular device driver probing starts. Michal Simek has the same
> issue in the zynq clock driver that you have for SMP initialization.
> We have talked about this with Mark Brown already, and I think we will
> find a solution for this in the end, but it's not as straightforward
> as I first hoped. We can probably use help in this area.

I wouldn't say issue because we have created workaround which should be acceptable.
For more info.
https://lkml.org/lkml/2014/1/6/349  patch 2/7 is that what we have done
to get it work.
Also I hope that this can go to mainline before any nice solution will be find
not to stop work on others drivers which use regmap.

But there is definitely a space for doing this better.


> 2. There is actually no reason for the SMP code to be called this early,
> and multiple platforms would like to move SMP init to a later stage.
> Stephen Boyd has recently started reworking the way we do SMP init,
> and he may have some more insight.
> 
> In the meantime, I'd suggest you do the binding under the assumption
> that it will work eventually, and then work around the current limitations
> in the SMP code by looking for the device nodes you need and map them
> manually, as you did in the previous versions of your patch set.

Yep, that's exactly what we have done just because of other driver developing
till this is resolved.

Thanks,
Michal

Re: [PATCH v3 7/7] ARM: brcmstb: dts: add a reference DTS for Broadcom 7445

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 762 bytes --]

On Thu, Jan 16, 2014 at 12:19:00PM +0100, Arnd Bergmann wrote:

> 1. Other platforms also require the syscon driver to be active before
> the regular device driver probing starts. Michal Simek has the same
> issue in the zynq clock driver that you have for SMP initialization.
> We have talked about this with Mark Brown already, and I think we will
> find a solution for this in the end, but it's not as straightforward
> as I first hoped. We can probably use help in this area.

I thought the solution with deferring registration of the resource for
dev_get_regmap() until a proper device materialised seemed simple and
enough, did you folks run into any problems with that?  I had assumed a
patch was likely to materialise so wasn't worrying about it myself.

[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 836 bytes --]

Re: [PATCH v3 7/7] ARM: brcmstb: dts: add a reference DTS for Broadcom 7445

[Arnd Bergmann]

On Thursday 16 January 2014, Mark Brown wrote:
> On Thu, Jan 16, 2014 at 12:19:00PM +0100, Arnd Bergmann wrote:
> 
> > 1. Other platforms also require the syscon driver to be active before
> > the regular device driver probing starts. Michal Simek has the same
> > issue in the zynq clock driver that you have for SMP initialization.
> > We have talked about this with Mark Brown already, and I think we will
> > find a solution for this in the end, but it's not as straightforward
> > as I first hoped. We can probably use help in this area.
> 
> I thought the solution with deferring registration of the resource for
> dev_get_regmap() until a proper device materialised seemed simple and
> enough, did you folks run into any problems with that?  I had assumed a
> patch was likely to materialise so wasn't worrying about it myself.

I'm still hoping that Michal will do that patch.

	Arnd

Re: [PATCH v3 7/7] ARM: brcmstb: dts: add a reference DTS for Broadcom 7445

[Michal Simek]

[-- Attachment #1: Type: text/plain, Size: 1349 bytes --]

On 01/17/2014 06:04 PM, Arnd Bergmann wrote:
> On Thursday 16 January 2014, Mark Brown wrote:
>> On Thu, Jan 16, 2014 at 12:19:00PM +0100, Arnd Bergmann wrote:
>>
>>> 1. Other platforms also require the syscon driver to be active before
>>> the regular device driver probing starts. Michal Simek has the same
>>> issue in the zynq clock driver that you have for SMP initialization.
>>> We have talked about this with Mark Brown already, and I think we will
>>> find a solution for this in the end, but it's not as straightforward
>>> as I first hoped. We can probably use help in this area.
>>
>> I thought the solution with deferring registration of the resource for
>> dev_get_regmap() until a proper device materialised seemed simple and
>> enough, did you folks run into any problems with that?  I had assumed a
>> patch was likely to materialise so wasn't worrying about it myself.
> 
> I'm still hoping that Michal will do that patch.

And what was the resolution/recommendation how to do it?

Thanks,
Michal


-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform



[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 263 bytes --]

Re: [PATCH v3 7/7] ARM: brcmstb: dts: add a reference DTS for Broadcom 7445

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 698 bytes --]

On Thu, Jan 23, 2014 at 09:58:21AM +0100, Michal Simek wrote:
> On 01/17/2014 06:04 PM, Arnd Bergmann wrote:

> >> I thought the solution with deferring registration of the resource for
> >> dev_get_regmap() until a proper device materialised seemed simple and
> >> enough, did you folks run into any problems with that?  I had assumed a
> >> patch was likely to materialise so wasn't worrying about it myself.

> > I'm still hoping that Michal will do that patch.

> And what was the resolution/recommendation how to do it?

Split the regmap creation so the managed resource registration could be
done later on with an already allocated regmap instead of requiring it
to be done at creation time.

[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 836 bytes --]