From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753540AbaIXRqI (ORCPT ); Wed, 24 Sep 2014 13:46:08 -0400 Received: from out3-smtp.messagingengine.com ([66.111.4.27]:56584 "EHLO out3-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752174AbaIXRqF (ORCPT ); Wed, 24 Sep 2014 13:46:05 -0400 X-Sasl-enc: c39eOcKzBVMUGvnW+hbuYahbft0EIzeHhSr4VuSMbOGq 1411580764 Date: Wed, 24 Sep 2014 14:45:57 -0300 From: Henrique de Moraes Holschuh To: Andy Lutomirski Cc: Borislav Petkov , Chuck Ebbert , "H. Peter Anvin" , "linux-kernel@vger.kernel.org" Subject: Re: x86, microcode: BUG: microcode update that changes x86_capability Message-ID: <20140924174557.GD31678@khazad-dum.debian.net> References: <20140919001311.GB5331@khazad-dum.debian.net> <20140919110014.GC29639@khazad-dum.debian.net> <20140919112953.GA3256@nazgul.tnic> <20140919075415.5149d5f2@as> <20140919150042.GC5318@nazgul.tnic> <20140919164217.GD17456@khazad-dum.debian.net> <20140923200054.GB16467@pd.tnic> <20140924145658.GB31678@khazad-dum.debian.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-GPG-Fingerprint1: 4096R/39CB4807 C467 A717 507B BAFE D3C1 6092 0BD9 E811 39CB 4807 X-GPG-Fingerprint2: 1024D/1CDB0FE3 5422 5C61 F6B7 06FB 7E04 3738 EE25 DE3F 1CDB 0FE3 User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 24 Sep 2014, Andy Lutomirski wrote: > On Wed, Sep 24, 2014 at 7:56 AM, Henrique de Moraes Holschuh > wrote: > > And I'd really prefer it to be "update x86_capability, warn the user and > > carry on" for anything that is not going to crash the kernel. Several > > distros will really want this backported to -stable, as the older kernels > > cannot do early microcode updates. > > > > I'm trying to see if Intel is willing to document any additional > controls for the TSX bits in this ucode. No word yet, but I might > hear something soon. If they do document it, please make sure to ask what will happen in the following situation: Assume there is a newer release of Intel microcode for these processors, i.e. newer than the microcodes in the 2014-09-13 release. IOW assume there are at least two public microcode updates in which the Intel TSX feature has been disabled by default, but can be enabled by the BIOS/UEFI. 1. BIOS/UEFI has recent microcode (which has the Intel TSX on/off switch), but it is not the latest microcode, and installed this update on the processor. 2. BIOS/UEFI has *enabled* Intel TSX on user request. 3. Microcode is updated to the latest microcode by the operating system, newer than the one in BIOS/UEFI. After step 3, will Intel TSX be enabled, or disabled ? Or, to be more explicit: will future microcode updates preserve Intel TSX enabled/disabled state, or will they always reset it to disabled? This is really important, for obvious reasons. -- "One disk to rule them all, One disk to find them. One disk to bring them all and in the darkness grind them. In the Land of Redmond where the shadows lie." -- The Silicon Valley Tarot Henrique Holschuh