From: Chris Wilson <chris@chris-wilson.co.uk>
To: Robert Bragg <robert@sixbynine.org>
Cc: linux-kernel@vger.kernel.org,
Peter Zijlstra <a.p.zijlstra@chello.nl>,
Paul Mackerras <paulus@samba.org>, Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Daniel Vetter <daniel.vetter@ffwll.ch>,
Rob Clark <robdclark@gmail.com>,
Samuel Pitoiset <samuel.pitoiset@gmail.com>,
Ben Skeggs <bskeggs@redhat.com>
Subject: Re: [RFC PATCH 3/3] i915: Expose PMU for Observation Architecture
Date: Thu, 23 Oct 2014 08:47:39 +0100 [thread overview]
Message-ID: <20141023074739.GH13512@nuc-i3427.alporthouse.com> (raw)
In-Reply-To: <1413991731-20628-4-git-send-email-robert@sixbynine.org>
On Wed, Oct 22, 2014 at 04:28:51PM +0100, Robert Bragg wrote:
> + /* XXX: Not sure that this is really acceptable...
> + *
> + * i915_gem_context.c currently owns pinning/unpinning legacy
> + * context buffers and although that code has a
> + * get_context_alignment() func to handle a different
> + * constraint for gen6 we are assuming it's fixed for gen7
> + * here. Another option besides pinning here would be to
> + * instead hook into context switching and update the
> + * OACONTROL configuration on the fly.
> + */
> + if (dev_priv->oa_pmu.specific_ctx) {
> + struct intel_context *ctx = dev_priv->oa_pmu.specific_ctx;
> + int ret;
> +
> + ret = i915_gem_obj_ggtt_pin(ctx->legacy_hw_ctx.rcs_state,
> + 4096, 0);
Right if you pin it here with a different alignment, when we try to pin
it with the required hw ctx alignment it will fail. Easiest way is to
record the ctx->legacy_hw_ctx.alignment and reuse that here.
> + if (ret) {
> + DRM_DEBUG_DRIVER("Couldn't pin %d\n", ret);
> + ret = -EBUSY;
As an exercise, think of all the possible error values from pin() and
tell me why overriding that here is a bad, bad idea.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
next prev parent reply other threads:[~2014-10-23 7:48 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-10-22 15:28 [RFC PATCH 0/3] Expose gpu counters via perf pmu driver Robert Bragg
2014-10-22 15:28 ` [RFC PATCH 1/3] perf: export perf_event_overflow Robert Bragg
2014-10-22 15:28 ` [RFC PATCH 2/3] perf: Add PERF_PMU_CAP_IS_DEVICE flag Robert Bragg
2014-10-22 15:28 ` [RFC PATCH 3/3] i915: Expose PMU for Observation Architecture Robert Bragg
2014-10-23 7:47 ` Chris Wilson [this message]
2014-10-24 2:33 ` Robert Bragg
2014-10-24 6:56 ` Chris Wilson
2014-10-23 5:58 ` [RFC PATCH 0/3] Expose gpu counters via perf pmu driver Ingo Molnar
2014-10-24 13:39 ` Robert Bragg
2014-10-30 19:08 ` Peter Zijlstra
2014-11-03 21:47 ` Robert Bragg
2014-11-05 12:33 ` Peter Zijlstra
2014-11-06 0:37 ` Robert Bragg
2014-11-10 11:13 ` Ingo Molnar
2014-11-12 23:33 ` Robert Bragg
2014-11-16 9:27 ` Ingo Molnar
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