From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754319AbbBKTfe (ORCPT ); Wed, 11 Feb 2015 14:35:34 -0500 Received: from mga14.intel.com ([192.55.52.115]:13796 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754028AbbBKTfd (ORCPT ); Wed, 11 Feb 2015 14:35:33 -0500 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.09,560,1418112000"; d="scan'208";a="676516519" Date: Wed, 11 Feb 2015 11:36:50 -0800 From: David Cohen To: Heikki Krogerus Cc: Felipe Balbi , Greg Kroah-Hartman , Baolu Lu , linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, Kishon Vijay Abraham I Subject: Re: [PATCH 8/8] phy: add driver for TI TUSB1210 ULPI PHY Message-ID: <20150211193650.GB28788@psi-dev26.jf.intel.com> References: <20150128142024.GA2378@kuha.fi.intel.com> <20150128180255.GA7551@psi-dev26.jf.intel.com> <20150129141412.GA2570@kuha.fi.intel.com> <20150129162023.GF21217@saruman.tx.rr.com> <20150130092956.GE2570@kuha.fi.intel.com> <20150130162038.GB20689@psi-dev26.jf.intel.com> <20150202125959.GB30962@kuha.fi.intel.com> <20150210190531.GC28827@psi-dev26.jf.intel.com> <20150210192350.GD28827@psi-dev26.jf.intel.com> <20150211131255.GA10985@kuha.fi.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20150211131255.GA10985@kuha.fi.intel.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Feb 11, 2015 at 03:12:55PM +0200, Heikki Krogerus wrote: > Hi David, Hi Heikki, > > > > > > In order for phy to be functional, it does not depend only on toggling > > > > > GPIOs. It depends on DWC3 going to reset state, then phy executes power > > > > > on sequence, then DWC3 going out of reset state to sync clocks with phy. > > > > > You're saying we should tell BIOS is concurrently mess with dwc3 > > > > > together with dwc3 driver? > > > > > > > > I don't understand what you are saying here? > > > > > > TUSB1210 needs to come out of reset only when DWC3 is in reset state. > > > This is how current code works in dwc3_core_soft_reset(): > > > - dwc3 goes to reset > > > - phy goes to reset > > > - phy gets out of reset > > > - dwc3 gets out of reset > > > > > > This is how you're proposing: > > > - phy goes to reset (DSDT code, when loading module) > > > - phy gets out of reset (DSDT code, when loading module) > > > > > > - dwc3 goes to reset (dwc3_core_soft_reset()) > > > - dwc3 gets our of reset (dwc3_core_soft_reset()) > > > > > > Felipe, do you see a problem with this new context? If not, I'm > > > satisfied with Heikki's ULPI bus proposal considering my comment below. > > > > Sorry, guess I spoke too soon :/ > > I am satisfied with the phy case, but I forgot about the chicken/egg > > problem I reported earlier: > > DWC3 will not be functional when reloading the module after it went to > > reset state. Then ULPI enumeration can't happen regardless DSDT code > > powered on phy. > > One point here. If we have DSDT handling the gpios with the operation > region, those gpio resources don't need to be given to any device > (actually I think they really shouldn't be given to anything in that > case). Agree with that. > > > Heikki, do you have a proposal for that? IMHO that's the main missing > > point if we forget about BYT-CR legacy. > > I'm sorry but I'm still not sure about the scenario you are talking > about. Probably because I'm asking this question in the wrong place. It is regarding patch 6/8. I resent the question there. Br, David