From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932341AbbBLMMX (ORCPT ); Thu, 12 Feb 2015 07:12:23 -0500 Received: from mga09.intel.com ([134.134.136.24]:49478 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932152AbbBLMMW (ORCPT ); Thu, 12 Feb 2015 07:12:22 -0500 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.09,565,1418112000"; d="scan'208";a="676891282" Date: Thu, 12 Feb 2015 14:12:14 +0200 From: Heikki Krogerus To: David Cohen Cc: Felipe Balbi , Greg Kroah-Hartman , Baolu Lu , linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 6/8] usb: dwc3: add ULPI interface support Message-ID: <20150212121214.GA18860@kuha.fi.intel.com> References: <1422025978-178336-1-git-send-email-heikki.krogerus@linux.intel.com> <1422025978-178336-7-git-send-email-heikki.krogerus@linux.intel.com> <20150211193419.GA28788@psi-dev26.jf.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20150211193419.GA28788@psi-dev26.jf.intel.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c > > index a8c9062..66cbf38 100644 > > --- a/drivers/usb/dwc3/core.c > > +++ b/drivers/usb/dwc3/core.c > > @@ -879,6 +879,10 @@ static int dwc3_probe(struct platform_device *pdev) > > platform_set_drvdata(pdev, dwc); > > dwc3_cache_hwparams(dwc); > > > > + ret = dwc3_ulpi_init(dwc); > > If I understood correctly, this call will result in enumerating the phy > via ULPI bus, then registering the correct ULPI device. > Can you guarantee ULPI will be always accessible at this point if we > remove dwc3 module and load it again? OK, got it. So yes, I can guarantee that ULPI will be acessible at this point. If we are in a state where we could soft reset dwc3, we know we can access ULPI. The fact that dwc3 itself expects to be able to write to the ULPI registers at that point guarantees it for us. So in practice when ever dwc3 is powered we will be able to access ULPI for as long as the USB2 PHY interface is not suspended separately with GUSB2PHYCFG SusPHY bit. And even then we would only need to resume it with the same bit and ULPI is accessible again. Cheers, -- heikki