From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755814AbbBLOZH (ORCPT ); Thu, 12 Feb 2015 09:25:07 -0500 Received: from hqemgate15.nvidia.com ([216.228.121.64]:7990 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756048AbbBLOZE (ORCPT ); Thu, 12 Feb 2015 09:25:04 -0500 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Thu, 12 Feb 2015 06:12:45 -0800 Date: Thu, 12 Feb 2015 16:24:40 +0200 From: Peter De Schrijver To: Mikko Perttunen CC: , , , , , , , , , , , , , , Tuomas Tynkkynen Subject: Re: [PATCH v7 07/16] clk: tegra: Save/restore CCLKG_BURST_POLICY on suspend Message-ID: <20150212142440.GL20811@tbergstrom-lnx.Nvidia.com> References: <1420723339-30735-1-git-send-email-mikko.perttunen@kapsi.fi> <1420723339-30735-8-git-send-email-mikko.perttunen@kapsi.fi> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <1420723339-30735-8-git-send-email-mikko.perttunen@kapsi.fi> X-NVConfidentiality: public User-Agent: Mutt/1.5.21 (2010-09-15) X-Originating-IP: [10.21.24.170] X-ClientProxiedBy: UKMAIL102.nvidia.com (10.26.138.15) To UKMAIL101.nvidia.com (10.26.138.13) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Jan 08, 2015 at 03:22:10PM +0200, Mikko Perttunen wrote: > From: Tuomas Tynkkynen > > Save and restore this register since the LP1 restore assembly routines > fiddle with it. Otherwise the CPU would keep running on PLLX after > resume from suspend even when DFLL was the original clocksource. > > Signed-off-by: Tuomas Tynkkynen > Signed-off-by: Mikko Perttunen Acked-By: Peter De Schrijver > --- > drivers/clk/tegra/clk-tegra124.c | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c > index 623b77f..9354c42 100644 > --- a/drivers/clk/tegra/clk-tegra124.c > +++ b/drivers/clk/tegra/clk-tegra124.c > @@ -89,6 +89,8 @@ > #define PMC_PLLM_WB0_OVERRIDE 0x1dc > #define PMC_PLLM_WB0_OVERRIDE_2 0x2b0 > > +#define CCLKG_BURST_POLICY 0x368 > + > #define UTMIP_PLL_CFG2 0x488 > #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6) > #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18) > @@ -121,6 +123,8 @@ > #ifdef CONFIG_PM_SLEEP > static struct cpu_clk_suspend_context { > u32 clk_csite_src; > + u32 cclkg_burst; > + u32 cclkg_divider; > } tegra124_cpu_clk_sctx; > #endif > > @@ -1331,12 +1335,22 @@ static void tegra124_cpu_clock_suspend(void) > tegra124_cpu_clk_sctx.clk_csite_src = > readl(clk_base + CLK_SOURCE_CSITE); > writel(3 << 30, clk_base + CLK_SOURCE_CSITE); > + > + tegra124_cpu_clk_sctx.cclkg_burst = > + readl(clk_base + CCLKG_BURST_POLICY); > + tegra124_cpu_clk_sctx.cclkg_divider = > + readl(clk_base + CCLKG_BURST_POLICY + 4); > } > > static void tegra124_cpu_clock_resume(void) > { > writel(tegra124_cpu_clk_sctx.clk_csite_src, > clk_base + CLK_SOURCE_CSITE); > + > + writel(tegra124_cpu_clk_sctx.cclkg_burst, > + clk_base + CCLKG_BURST_POLICY); > + writel(tegra124_cpu_clk_sctx.cclkg_divider, > + clk_base + CCLKG_BURST_POLICY + 4); > } > #endif > > -- > 2.2.1 >