Re: [PATCH RFC v9 01/20] clk: divider: Correct parent clk round rate if no bestdiv is normally found

From: Sascha Hauer <s.hauer@pengutronix.de>
To: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: Russell King - ARM Linux <linux@arm.linux.org.uk>,
	Liu Ying <Ying.Liu@freescale.com>,
	dri-devel@lists.freedesktop.org, stefan.wahren@i2se.com,
	devicetree@vger.kernel.org, kernel@pengutronix.de,
	sboyd@codeaurora.org, linux-kernel@vger.kernel.org,
	a.hajda@samsung.com, andy.yan@rock-chips.com,
	mturquette@linaro.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH RFC v9 01/20] clk: divider: Correct parent clk round rate if no bestdiv is normally found
Date: Fri, 13 Feb 2015 19:57:13 +0100	[thread overview]
Message-ID: <20150213185713.GA12209@pengutronix.de> (raw)
In-Reply-To: <54DE0BB8.7070004@ti.com>

On Fri, Feb 13, 2015 at 04:35:36PM +0200, Tomi Valkeinen wrote:
> On 12/02/15 15:41, Sascha Hauer wrote:
> 
> > Tomis patch is based on the assumption that clk_set_rate(clk_round_rate(rate))
> > is equal to clk_round_rate(rate). So when this assumption is wrong then
> > it should simply be reverted.
> 
> When is it not equal?
> 
> I agree that doing clk_set_rate(clk, clk_round_rate(clk, rate)) is
> pointless, but shouldn't it still work?
> 
> And we can forget about clk_round_rate. Without my patch, this would
> behave oddly also:
> 
> rate = clk_get_rate(clk);
> clk_set_rate(clk, rate);
> 
> The end result could be something else than 'rate'.

I agree that it's a bit odd, but I think it has to be like this.
Consider that you request a rate of 100Hz, but the clock can only
produce 99.5Hz, so due to rounding clk_round_rate() returns 99Hz.
Now when you request 99Hz from clk_set_rate() the 99.5Hz value
can't be used because it's too high.

Sascha

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