From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753773AbbBMWCM (ORCPT ); Fri, 13 Feb 2015 17:02:12 -0500 Received: from mga02.intel.com ([134.134.136.20]:5634 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753281AbbBMWCK (ORCPT ); Fri, 13 Feb 2015 17:02:10 -0500 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.09,573,1418112000"; d="scan'208";a="677725980" Date: Fri, 13 Feb 2015 14:03:45 -0800 From: David Cohen To: Heikki Krogerus Cc: Felipe Balbi , Greg Kroah-Hartman , Baolu Lu , linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 6/8] usb: dwc3: add ULPI interface support Message-ID: <20150213220345.GB25281@psi-dev26.jf.intel.com> References: <1422025978-178336-1-git-send-email-heikki.krogerus@linux.intel.com> <1422025978-178336-7-git-send-email-heikki.krogerus@linux.intel.com> <20150211193419.GA28788@psi-dev26.jf.intel.com> <20150212121214.GA18860@kuha.fi.intel.com> <20150213014130.GC21337@psi-dev26.jf.intel.com> <20150213131640.GC27695@kuha.fi.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20150213131640.GC27695@kuha.fi.intel.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Heikki, On Fri, Feb 13, 2015 at 03:16:40PM +0200, Heikki Krogerus wrote: > On Thu, Feb 12, 2015 at 05:41:30PM -0800, David Cohen wrote: > > On Thu, Feb 12, 2015 at 02:12:14PM +0200, Heikki Krogerus wrote: > > > > > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c > > > > > index a8c9062..66cbf38 100644 > > > > > --- a/drivers/usb/dwc3/core.c > > > > > +++ b/drivers/usb/dwc3/core.c > > > > > @@ -879,6 +879,10 @@ static int dwc3_probe(struct platform_device *pdev) > > > > > platform_set_drvdata(pdev, dwc); > > > > > dwc3_cache_hwparams(dwc); > > > > > > > > > > + ret = dwc3_ulpi_init(dwc); > > > > > > > > If I understood correctly, this call will result in enumerating the phy > > > > via ULPI bus, then registering the correct ULPI device. > > > > Can you guarantee ULPI will be always accessible at this point if we > > > > remove dwc3 module and load it again? > > > > > > OK, got it. So yes, I can guarantee that ULPI will be acessible at > > > this point. If we are in a state where we could soft reset dwc3, we > > > know we can access ULPI. The fact that dwc3 itself expects to be able > > > to write to the ULPI registers at that point guarantees it for us. > > > > I just double checked DWC3 TRM. > > You are correct, by the time we're executing dwc3_core_soft_reset() ULPI > > bus is already accessible. But the TRM also specifies an ULPI phy would > > be reset by DCTL's core soft reset, which is executed by dwc3_core_init() > > before calling dwc3_core_soft_reset(). It does mention DWC3 writes data > > to an ULPI phy register during reset, but it also mentions the clock > > sync happens during that time. > > > > That makes no even OK, but more correct IMO to power on phy before > > core's soft reset (i.e. by ACPI methods). But it lets us in a grey area > > whether ULPI is reliably accessible before core's soft reset. > > > > I believe if you move the dwc3_ulpi_init() to dwc3_core_init(), after > > core's soft reset we've got no more grey area. > > Well, we have already requested the phys in dwc3_probe before that so > some refactoring will be needed. It's probable no a problem. Sounds good :) > > Btw, I'm sorry about telling this so late, but I'm going to be on > vacation for the next two weeks. Thanks for the notice. Br, David > > > Cheers, > > -- > heikki