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Date: Mon, 16 Feb 2015 17:49:20 +0100
From: Maxime Ripard <maxime.ripard@free-electrons.com>
To: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Cc: Gregory Clement <gregory.clement@free-electrons.com>,
        Jason Cooper <jason@lakedaemon.net>, Andrew Lunn <andrew@lunn.ch>,
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        Sudhakar Gundubogula <sudhakar@marvell.com>,
        Seif Mazareeb <seif@marvell.com>, stable@vger.kernel.org
Subject: Re: [PATCH v3 1/2] mtd: nand: pxa3xx: Fix PIO FIFO draining
Message-ID: <20150216164920.GF25269@lukather>
References: <1424091072-7738-1-git-send-email-maxime.ripard@free-electrons.com>
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On Mon, Feb 16, 2015 at 10:35:50AM -0300, Ezequiel Garcia wrote:
> On 02/16/2015 09:51 AM, Maxime Ripard wrote:
> > The NDDB register holds the data that are needed by the read and write
> > commands.
> >=20
> > However, during a read PIO access, the datasheet specifies that after e=
ach 32
> > bits read in that register, when BCH is enabled, we have to make sure t=
hat the
> > RDDREQ bit is set in the NDSR register.
> >=20
>=20
> Typo s/32 bits/32 bytes

Good catch, thanks!
Maxime

--=20
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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