From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754940AbbCIQQt (ORCPT ); Mon, 9 Mar 2015 12:16:49 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:42260 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753663AbbCIQQr (ORCPT ); Mon, 9 Mar 2015 12:16:47 -0400 Date: Mon, 9 Mar 2015 11:16:08 -0500 From: Felipe Balbi To: Linus Walleij CC: David Cohen , Robert Baldyga , Heikki Krogerus , MyungJoo Ham , Chanwoo Choi , "linux-kernel@vger.kernel.org" , "linux-usb@vger.kernel.org" , , Felipe Balbi Subject: Re: [PATCH v2] extcon: otg_gpio: add driver for USB OTG port controlled by GPIO(s) Message-ID: <20150309161608.GF3739@saruman.tx.rr.com> Reply-To: References: <1419288217-19262-1-git-send-email-david.a.cohen@linux.intel.com> <1424375984-26241-1-git-send-email-david.a.cohen@linux.intel.com> <54E6D721.9070107@samsung.com> <20150220191700.GB15303@psi-dev26.jf.intel.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="0hHDr/TIsw4o3iPK" Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --0hHDr/TIsw4o3iPK Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Sat, Mar 07, 2015 at 09:06:22PM +0100, Linus Walleij wrote: > On Fri, Feb 20, 2015 at 8:17 PM, David Cohen > wrote: > > On Fri, Feb 20, 2015 at 10:53:44AM +0100, Linus Walleij wrote: >=20 > >> I would put this adjacent to the phy driver somewhere in drivers/usb/* > >> and make the actual USB-driver thing handle its GPIOs directly. > >> But I guess David and Felipe have already discussed that as we're > >> seeing this patch? > > > > - The mux functions would be controlled by a possible new pinctrl-gpio > > driver (Linus, your input here would be nice :) >=20 > I don't understand what this means, does it mean a pin control function > somewhere else controlled by a GPIO pin? >=20 > Or do you mean a new combined pin control and GPIO driver (we have > plenty of these). >=20 > If you elaborate on what you need to do in that driver I might > understand it better. there's a discrete mux (not something integrated in the SoC) whose select signal is tied to a GPIO (in some cases, more than one, but usually people use 2-state muxes). --=20 balbi --0hHDr/TIsw4o3iPK Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBAgAGBQJU/cdIAAoJEIaOsuA1yqREIKgP/2vCIcfCInnNnMVVeXp0kGmX Qco7bIu4KsBfiXG3BHdra+3dXP/siXBoTZt/SBn71U9rocR48FNPEnd364QSCJlo Ofnr7fGNP4W6liqP0z9YOoQD0dPEyiUy/9AOPpx+EfHCzP13pZbC1ez/0438S0EC TXT7pfEM+NPHqyYohXvYC7BUM6ZqIGmWM2PFYHQtkWLh5mKut8qZzbrFBZsKZaIQ Ov7F/iyL0LgxQWVPmSD3VL4Z8VXPBVD0Uzpmf8g0QQtp/wQaDLKk4J+vuIuhehld Op7asnZFqkwvEJI667jfwiwwA/B3wm1JrR/otIcT58ANw4JJc2xdTFK5Z38lhxM6 N3pnl+H/0FBI3584kaV7fwI7VAsGREFK05U7aiB9Kozoou/rHTGDcpI9kYdwhqn7 lYIlrwnvr6zwrUTHXgRGY/epOMaiPKBD+oCMTxTTQSof9WeIG120vfd0BsHYbfHU /U60Xc0bOAGxyBpEJuocwSjaO6274/NQ4rrtThk1d9w+0KBvjaOs0vJk0b3kYCpT 8E4iED1Drhqv8+UR46xbFBmhlrlIC6zkXIY28a3AzPPKKqIjuwy/0VOZwJ2deVoI +dJBAH3Y+xPkz+pEHPNXOvQkt6m4cV/MxWIOeH9mlCoHoqdc7BLqagXpwbfTkEH5 d0b4J8iAPb7rVZSgNfqS =Gaug -----END PGP SIGNATURE----- --0hHDr/TIsw4o3iPK--