From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932113AbbCaOAn (ORCPT ); Tue, 31 Mar 2015 10:00:43 -0400 Received: from eddie.linux-mips.org ([148.251.95.138]:58168 "EHLO cvs.linux-mips.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752386AbbCaOAj (ORCPT ); Tue, 31 Mar 2015 10:00:39 -0400 Date: Tue, 31 Mar 2015 16:00:34 +0200 From: Ralf Baechle To: Andrew Bresticker Cc: Linus Walleij , Alexandre Courbot , devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Ezequiel Garcia , James Hartley , James Hogan Subject: Re: [PATCH V2 0/3] pinctrl: Support for IMG Pistachio Message-ID: <20150331140034.GE28951@linux-mips.org> References: <1427757416-14491-1-git-send-email-abrestic@chromium.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1427757416-14491-1-git-send-email-abrestic@chromium.org> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Mar 30, 2015 at 04:16:53PM -0700, Andrew Bresticker wrote: > This series adds support for the system pin and GPIO controller on the IMG > Pistachio SoC. Pistachio's system pin controller manages 99 pins, 90 of > which are MFIOs which can be muxed between multiple functions or used > as GPIOs. The GPIO control for the 90 MFIOs is broken up into banks > of 16. Pistachio also has a second pin controller, the RPU pin controller, > which will be supported by a future patchset through an extension to this > driver. > > Test on an IMG Pistachio BuB. Based on mips-for-linux-next which inluces my > series adding Pistachio platform support [1]. A branch with this series is > available at [2]. Does this mean you want me to funnel this through the MIPS tree? If so, could I have an Ack from the maintainers? Thanks, Ralf