From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932687AbbDIIoD (ORCPT ); Thu, 9 Apr 2015 04:44:03 -0400 Received: from mail-wi0-f170.google.com ([209.85.212.170]:34784 "EHLO mail-wi0-f170.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932405AbbDIIn5 (ORCPT ); Thu, 9 Apr 2015 04:43:57 -0400 Date: Thu, 9 Apr 2015 10:43:54 +0200 From: Thierry Reding To: Liu Ying Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux@arm.linux.org.uk, kernel@pengutronix.de, p.zabel@pengutronix.de, shawn.guo@linaro.org, mturquette@linaro.org, airlied@linux.ie, andy.yan@rock-chips.com, stefan.wahren@i2se.com, a.hajda@samsung.com, sboyd@codeaurora.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH RFC v9 11/20] drm/bridge: Add Synopsys DesignWare MIPI DSI host controller driver Message-ID: <20150409084353.GD12103@ulmo> References: <1423720903-24806-1-git-send-email-Ying.Liu@freescale.com> <1423720903-24806-12-git-send-email-Ying.Liu@freescale.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="Hf61M2y+wYpnELGG" Content-Disposition: inline In-Reply-To: <1423720903-24806-12-git-send-email-Ying.Liu@freescale.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --Hf61M2y+wYpnELGG Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Thu, Feb 12, 2015 at 02:01:34PM +0800, Liu Ying wrote: [...] > diff --git a/drivers/gpu/drm/bridge/dw_mipi_dsi.c b/drivers/gpu/drm/bridge/dw_mipi_dsi.c [...] > +struct dw_mipi_dsi { > + struct mipi_dsi_host dsi_host; > + struct drm_connector connector; > + struct drm_encoder *encoder; > + struct drm_bridge *bridge; > + struct drm_panel *panel; > + struct device *dev; > + > + void __iomem *base; > + > + struct clk *pllref_clk; > + struct clk *cfg_clk; > + struct clk *pclk; > + > + unsigned int lane_mbps; /* per lane */ > + u32 channel; > + u32 lanes; > + u32 format; > + struct drm_display_mode *mode; > + > + const struct dw_mipi_dsi_plat_data *pdata; > + > + bool enabled; > +}; While reviewing this I kept thinking whether this is really the right architectural design. This driver is a MIPI DSI host, a connector and a bridge, all in one. But it seems to me like it should really be an encoder/connector and a MIPI DSI host. Why the need for a bridge? The bridge abstraction targets blocks outside of the SoC, but it is my understanding that these DesignWare IP blocks are designed into SoCs. Thierry --Hf61M2y+wYpnELGG Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABCAAGBQJVJjvGAAoJEN0jrNd/PrOhXu8P/3FQzro+kD5l1BNexrccOlIu 2T+Fj0ezDjbaaJiVP+v/dZ4xzPmM3EFczq5xsL7gC1r0ehfm9yHJz1qFAh85Fp/0 7MGFdUl22/CiBbseAwm4/wlijIu1XxBxO7++ayZSxAWs1ZDz7hBvsH7OxVmlyYsk KHV6raVPGkqWmgWqzAt9mHtCL/zi5e0uyyxC6THWn0WzYfYkvWubflmeCUqDZ4ia XI9kJ850vlilcobtOeL0mqPeYKUvySZ8Rd141xc6HY/xpWZu7gZ2UY4xxwE+LQTB 65DQvLdyD7dKQjFuFjsCJ1sBUsFFvF9Q5MNbIZKf+dHeIMXiGODW71Sn5HQUOt0J dJbjAMvgfyr6MFFA0wkfWCdB58MjbWs8HPTzQOSczDGnZTPQfli68ACF5F5FKxfn Df9blYjrAvDQXZ+Uffk+auYYmjj0wfhVu+rkuv2icrH+iuj3zHRgP2d/TzH4wgfq 3d/14ApYVTcgNn+/OzN3ouAtZ9AQ6VR0SmwsP/YYMsZCYBRMtPyzmgqnBOezinox I/HwzXOd83aFhi8e7iTMMnybYPaYukMsbu0srKuyiA1vK5vG/buCZfnVKAl8KhJn KrVk10ffMCu7AWP4Y9KHxaTWeZ73J9ZWE87cojXlyMM2KcsKNcmFagGehLjxbCub RLqTtgBB/X6Tl6Z013xu =zGwb -----END PGP SIGNATURE----- --Hf61M2y+wYpnELGG--