From: Mark Rutland <mark.rutland@arm.com>
To: Daniel Thompson <daniel.thompson@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>,
"linaro-kernel@lists.linaro.org" <linaro-kernel@lists.linaro.org>,
Russell King <linux@arm.linux.org.uk>,
"patches@linaro.org" <patches@linaro.org>,
Marc Zyngier <Marc.Zyngier@arm.com>,
Stephen Boyd <sboyd@codeaurora.org>,
Will Deacon <Will.Deacon@arm.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Steven Rostedt <rostedt@goodmis.org>,
Daniel Drake <drake@endlessm.com>,
Dmitry Pervushin <dpervushin@gmail.com>,
Dirk Behme <dirk.behme@de.bosch.com>,
John Stultz <john.stultz@linaro.org>,
Tim Sander <tim@krieglstein.org>,
Catalin Marinas <Catalin.Marinas@arm.com>,
Sumit Semwal <sumit.semwal@linaro.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [RESEND PATCH 4.0-rc7 v20 3/6] irqchip: gic: Introduce plumbing for IPI FIQ
Date: Wed, 22 Apr 2015 11:38:41 +0100 [thread overview]
Message-ID: <20150422103841.GC27345@leverpostej> (raw)
In-Reply-To: <5536BDE8.2030403@linaro.org>
> > I just gave this a spin on my (non-MCPM) TC2, and secondaries don't come
> > up:
> >
> > CPU1: failed to boot: -38
> > CPU2: failed to boot: -38
> > CPU3: failed to boot: -38
> > CPU4: failed to boot: -38
> > Brought up 1 CPUs
> > SMP: Total of 1 processors activated (48.00 BogoMIPS).
> >
> > I tried investigating with a debugger. The unbooted CPUs look to be
> > stuck at the FW's spin loop, but the text doesn't look right (I see a
> > load of ADDEQ r0, r0, r0, #LSL 1 where there was previously a WFI loop).
> > That could be a bug with my debugger though.
> >
> > If I pause the CPUs at the right point, they sometimes enter the kernel
> > successfully. I don't have a good explanation for that.
> >
> > [...]
>
> Rats!
>
> I presume it is patch 3 that causes the regression? Patch 3 is the one
> that causes the GIC to adopt a different configuration if it find the
> kernel running in secure world (it sets all interrupts to group 1 and
> routes group 0 to FIQ).
>
> I only ask because it isn't until patch 6 that we actually place any
> interrupt sources into group 0.
Patch 3 appears to be to blame. I see the issue with patches 1-3 alone
applied atop of v4.0. With patch 3 reverted secondaries come up as
expected.
> >> @@ -427,6 +535,7 @@ static void gic_cpu_init(struct gic_chip_data *gic)
> >> void __iomem *base = gic_data_cpu_base(gic);
> >> unsigned int cpu_mask, cpu = smp_processor_id();
> >> int i;
> >> + unsigned long secure_irqs, secure_irq;
> >
> > I think secure_irq(s) is a misnomer here. It's just a mask of FIQ bits.
>
> I guess so, on GICv2 without security extentions these are not secure
> irqs. This is one of the places were IRQ, FIQ, irq and hwirq meet
> together and naming things is hard.
>
> What sort of name do you like: fiq(s), fiq_hwirq(s)?
I'd go for fiq_mask and fiq, or group1_mask and group1_irq.
[...]
> >> @@ -445,6 +554,20 @@ static void gic_cpu_init(struct gic_chip_data *gic)
> >>
> >> gic_cpu_config(dist_base, NULL);
> >>
> >> + /*
> >> + * If the distributor is configured to support interrupt grouping
> >> + * then set any PPI and SGI interrupts not set in SMP_IPI_FIQ_MASK
> >> + * to be group1 and ensure any remaining group 0 interrupts have
> >> + * the right priority.
> >> + */
> >> + if (GICD_ENABLE_GRP1 & readl_relaxed(dist_base + GIC_DIST_CTRL)) {
> >> + secure_irqs = SMP_IPI_FIQ_MASK;
> >> + writel_relaxed(~secure_irqs, dist_base + GIC_DIST_IGROUP + 0);
> >> + gic->igroup0_shadow = ~secure_irqs;
> >> + for_each_set_bit(secure_irq, &secure_irqs, 16)
> >> + gic_set_group_irq(gic, secure_irq, 0);
> >> + }
> >
> > This only pokes GICD registers. Why isn't this in gic_dist_init?
>
> GIC_DIST_IGROUP[0] (which controls grouping for SGIs and PPIs) is banked
> per-cpu and form part of the per-cpu configuration.
Ah. Would you mind adding a note to the comment w.r.t. GICD_IGROUPR0
being banked per-cpu? I suspect I won't be the only one who fails to
recall that being the case.
We might want to rethink the gic_dist_init/gic_cpu_init naming if
they're no longer cleanly split across distributor and cpu interface
initialisation.
Thanks,
Mark.
next prev parent reply other threads:[~2015-04-22 10:38 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-03-24 16:53 [PATCH 4.0-rc5 v19 0/6] irq/arm: Implement arch_trigger_all_cpu_backtrace Daniel Thompson
2015-03-24 16:53 ` [PATCH 4.0-rc5 v19 1/6] irqchip: gic: Optimize locking in gic_raise_softirq Daniel Thompson
2015-03-24 16:53 ` [PATCH 4.0-rc5 v19 2/6] irqchip: gic: Make gic_raise_softirq FIQ-safe Daniel Thompson
2015-03-24 16:53 ` [PATCH 4.0-rc5 v19 3/6] irqchip: gic: Introduce plumbing for IPI FIQ Daniel Thompson
2015-03-24 16:53 ` [PATCH 4.0-rc5 v19 4/6] printk: Simple implementation for NMI backtracing Daniel Thompson
2015-03-24 16:53 ` [PATCH 4.0-rc5 v19 5/6] x86/nmi: Use common printk functions Daniel Thompson
2015-03-24 16:53 ` [PATCH 4.0-rc5 v19 6/6] ARM: Add support for on-demand backtrace of other CPUs Daniel Thompson
2015-04-07 15:37 ` [RESEND PATCH 4.0-rc5 v19 0/6] irq/arm: Implement arch_trigger_all_cpu_backtrace Daniel Thompson
2015-04-07 15:37 ` [RESEND PATCH 4.0-rc5 v19 1/6] irqchip: gic: Optimize locking in gic_raise_softirq Daniel Thompson
2015-04-07 15:37 ` [RESEND PATCH 4.0-rc5 v19 2/6] irqchip: gic: Make gic_raise_softirq FIQ-safe Daniel Thompson
2015-04-07 15:38 ` [RESEND PATCH 4.0-rc5 v19 3/6] irqchip: gic: Introduce plumbing for IPI FIQ Daniel Thompson
2015-04-07 15:38 ` [RESEND PATCH 4.0-rc5 v19 4/6] printk: Simple implementation for NMI backtracing Daniel Thompson
2015-04-07 15:38 ` [RESEND PATCH 4.0-rc5 v19 5/6] x86/nmi: Use common printk functions Daniel Thompson
2015-04-07 16:19 ` Steven Rostedt
2015-04-07 16:37 ` Borislav Petkov
2015-04-07 16:43 ` Steven Rostedt
2015-04-08 12:08 ` Daniel Thompson
2015-04-07 15:38 ` [RESEND PATCH 4.0-rc5 v19 6/6] ARM: Add support for on-demand backtrace of other CPUs Daniel Thompson
2015-04-10 9:51 ` [RESEND PATCH 4.0-rc7 v20 0/6] irq/arm: Implement arch_trigger_all_cpu_backtrace Daniel Thompson
2015-04-10 9:51 ` [RESEND PATCH 4.0-rc7 v20 1/6] irqchip: gic: Optimize locking in gic_raise_softirq Daniel Thompson
2015-04-21 12:51 ` Marc Zyngier
2015-04-10 9:51 ` [RESEND PATCH 4.0-rc7 v20 2/6] irqchip: gic: Make gic_raise_softirq FIQ-safe Daniel Thompson
2015-04-21 12:54 ` Marc Zyngier
2015-04-10 9:51 ` [RESEND PATCH 4.0-rc7 v20 3/6] irqchip: gic: Introduce plumbing for IPI FIQ Daniel Thompson
2015-04-21 13:45 ` Marc Zyngier
2015-04-21 21:03 ` Daniel Thompson
2015-04-22 9:15 ` Marc Zyngier
2015-04-22 12:45 ` Daniel Thompson
2015-04-22 12:57 ` Marc Zyngier
2015-04-22 15:40 ` Daniel Thompson
2015-04-21 14:50 ` Mark Rutland
2015-04-21 21:15 ` Daniel Thompson
2015-04-22 10:38 ` Mark Rutland [this message]
2015-07-02 13:31 ` Daniel Thompson
2015-04-10 9:51 ` [RESEND PATCH 4.0-rc7 v20 4/6] printk: Simple implementation for NMI backtracing Daniel Thompson
2015-04-10 9:51 ` [RESEND PATCH 4.0-rc7 v20 5/6] x86/nmi: Use common printk functions Daniel Thompson
2015-04-10 9:51 ` [RESEND PATCH 4.0-rc7 v20 6/6] ARM: Add support for on-demand backtrace of other CPUs Daniel Thompson
2015-04-10 10:47 ` [RESEND PATCH 4.0-rc7 v20 0/6] irq/arm: Implement arch_trigger_all_cpu_backtrace Daniel Thompson
2015-04-21 12:46 ` Thomas Gleixner
2015-04-21 13:08 ` Marc Zyngier
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