From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933703AbbENKRr (ORCPT ); Thu, 14 May 2015 06:17:47 -0400 Received: from mail-bn1on0141.outbound.protection.outlook.com ([157.56.110.141]:3901 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S932561AbbENKRm (ORCPT ); Thu, 14 May 2015 06:17:42 -0400 Authentication-Results: spf=none (sender IP is 165.204.84.221) smtp.mailfrom=amd.com; alien8.de; dkim=none (message not signed) header.d=none; X-WSS-ID: 0NOC4LC-07-NJ9-02 X-M-MSG: Date: Thu, 14 May 2015 18:17:28 +0800 From: Huang Rui To: Borislav Petkov CC: Len Brown , "Rafael J. Wysocki" , , Fengguang Wu , "Aaron Lu" , Tony Li , Thomas Gleixner Subject: Re: Mwait usage on AMD processors Message-ID: <20150514101727.GA6552@hr-slim.amd.com> References: <20150514065451.GA29830@hr-slim.amd.com> <20150514092137.GA29235@pd.tnic> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20150514092137.GA29235@pd.tnic> User-Agent: Mutt/1.5.21 (2010-09-15) X-EOPAttributedMessage: 0 X-Microsoft-Exchange-Diagnostics: 1;BY2FFO11FD044;1:/2Q3nHQJ6W+8IXZz3mkYV6R3TRxDIezyInx0TVpnbyWa4SN+lcYawTJcosjVFRS+SqsWoIp9v88oGBLXDs/57QWUCNkJR7BYX1bL/94pD8ygRaVndj96uXYIIl67MnCS+AOdmXv0TJDqsFba4RurkPBH3IxIHCkthB2hZAypcn7rqacIP/S9IAhLwmxhO1QcmRDvTuEIqtwz5cFQ9ngm84U6EXn8/E6d/WQpy1yEah2ewnV1AYa3Lbbg+TKTsaEJTtXWWXVgD8lRkfwoRdQexySt6kkJHvsflEg+QA6r6dk= X-Forefront-Antispam-Report: CIP:165.204.84.221;CTRY:US;IPV:NLI;EFV:NLI;SFV:NSPM;SFS:(10019020)(6009001)(428002)(24454002)(51704005)(164054003)(189002)(199003)(106466001)(50466002)(87936001)(33656002)(86362001)(46406003)(97756001)(54356999)(76176999)(50986999)(47776003)(4001350100001)(83506001)(62966003)(77156002)(23726002)(92566002)(53416004)(77096005)(189998001)(101416001)(2950100001)(46102003)(105586002)(110136002);DIR:OUT;SFP:1102;SCL:1;SRVR:BN1PR02MB069;H:atltwp01.amd.com;FPR:;SPF:None;MLV:sfv;MX:1;A:1;LANG:en; X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BN1PR02MB069; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(601004)(5005006)(3002001);SRVR:BN1PR02MB069;BCL:0;PCL:0;RULEID:;SRVR:BN1PR02MB069; X-Forefront-PRVS: 0576145E86 X-OriginatorOrg: amd4.onmicrosoft.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 May 2015 10:17:38.5394 (UTC) X-MS-Exchange-CrossTenant-Id: fde4dada-be84-483f-92cc-e026cbee8e96 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=fde4dada-be84-483f-92cc-e026cbee8e96;Ip=[165.204.84.221];Helo=[atltwp01.amd.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN1PR02MB069 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, May 14, 2015 at 11:21:37AM +0200, Borislav Petkov wrote: > On Thu, May 14, 2015 at 02:54:52PM +0800, Huang Rui wrote: > > Hi Len, Rafael, and all, > > > > AMD proposed a new instruction named mwaitx. This is an extension of > > mwait with a configurable timer (mwaitx = mwait + timer). And mwaitx > > will act as mwait if timer is disabled. However, mwait/mwaitx cannot > > let cpu core go to C1 state at current AMD processors, but has less > > power consumption even at C0 while core is waiting. > > As you know, mwait/mwaitx would have better performance than halt. So > > could we propose an implementation to use mwaitx at idle call in boot > > phase and cpuidle driver after boot phase. > > I'd select it in select_idle_routine()... > I know, actually, I already completed it in my local side, and mwaitx_idle will be called with x86_idle at boot phase. :) I plan to continue to implement it with cpuidle driver if mwaitx_idle can be accepted. > > And the mwaitx idle is exposed to user as an optional kernel > > parameter(idle=...), and decided by user. > > If MWAITX is better than C1 (and C1E, which we're doing now AFAIR) > then I'd enable it by default on those machines so that it is used > automatically. > At current processors, MWAITX cannot go to C1 state, but has faster waiting exit speed. MWAITX is still at C0 but less power consumption. So for now, I just want to set it optionally. HW designer will do deeper low power state (C1, and more) in future processors. At that time, we can enable it by default. Thanks, Rui