From: Maxime Ripard <maxime.ripard@free-electrons.com>
To: Chen-Yu Tsai <wens@csie.org>
Cc: Nicolas Pitre <nicolas.pitre@linaro.org>,
Dave Martin <Dave.Martin@arm.com>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com
Subject: Re: [RFC 2/7] ARM: dts: sun9i: Add CCI-400 device nodes for A80
Date: Sun, 17 May 2015 16:51:46 +0200 [thread overview]
Message-ID: <20150517145146.GK4004@lukather> (raw)
In-Reply-To: <1431583811-25780-3-git-send-email-wens@csie.org>
[-- Attachment #1: Type: text/plain, Size: 1890 bytes --]
On Thu, May 14, 2015 at 02:10:06PM +0800, Chen-Yu Tsai wrote:
> The A80 includes an ARM CCI-400 interconnect to support multi-cluster
> CPU caches.
>
> Also add the default clock frequency for the CPUs.
>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
> arch/arm/boot/dts/sun9i-a80.dtsi | 46 ++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 46 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
> index ca272e92b85d..200e712fbf0e 100644
> --- a/arch/arm/boot/dts/sun9i-a80.dtsi
> +++ b/arch/arm/boot/dts/sun9i-a80.dtsi
> @@ -58,48 +58,64 @@
> cpu0: cpu@0 {
> compatible = "arm,cortex-a7";
> device_type = "cpu";
> + cci-control-port = <&cci_control0>;
> + clock-frequency = <12000000>;
> reg = <0x0>;
> };
>
> cpu1: cpu@1 {
> compatible = "arm,cortex-a7";
> device_type = "cpu";
> + cci-control-port = <&cci_control0>;
> + clock-frequency = <12000000>;
> reg = <0x1>;
> };
>
> cpu2: cpu@2 {
> compatible = "arm,cortex-a7";
> device_type = "cpu";
> + cci-control-port = <&cci_control0>;
> + clock-frequency = <12000000>;
> reg = <0x2>;
> };
>
> cpu3: cpu@3 {
> compatible = "arm,cortex-a7";
> device_type = "cpu";
> + cci-control-port = <&cci_control0>;
> + clock-frequency = <12000000>;
> reg = <0x3>;
> };
>
> cpu4: cpu@100 {
> compatible = "arm,cortex-a15";
> device_type = "cpu";
> + cci-control-port = <&cci_control1>;
> + clock-frequency = <9000000>;
Isn't the clock frequency property is supposed to be the maximum
frequency of that CPU in Linux?
It looks odd that the A15 are clocked at a lower frequency than the
A7...
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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next prev parent reply other threads:[~2015-05-17 19:00 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-05-14 6:10 [RFC 0/7] ARM: sun9i: SMP support with Multi-Cluster Power Management Chen-Yu Tsai
2015-05-14 6:10 ` [RFC 1/7] ARM: sun9i: Support SMP on A80 with Multi-Cluster Power Management (MCPM) Chen-Yu Tsai
2015-05-14 6:10 ` [RFC 2/7] ARM: dts: sun9i: Add CCI-400 device nodes for A80 Chen-Yu Tsai
2015-05-17 14:51 ` Maxime Ripard [this message]
2015-05-19 7:12 ` Chen-Yu Tsai
2015-05-14 6:10 ` [RFC 3/7] ARM: dts: sun9i: Add CPUCFG device node for A80 dtsi Chen-Yu Tsai
2015-05-14 6:10 ` [RFC 4/7] ARM: dts: sun9i: Add PRCM device node for the " Chen-Yu Tsai
2015-05-17 14:54 ` Maxime Ripard
2015-05-19 3:08 ` Chen-Yu Tsai
2015-05-14 6:10 ` [RFC 5/7] ARM: sunxi: mcpm: Support CPU/cluster power down and hotplugging for cpu1~7 Chen-Yu Tsai
2015-05-14 6:10 ` [RFC 6/7] ARM: sunxi: mcpm: Support cpu0 hotplug Chen-Yu Tsai
2015-05-14 6:10 ` [RFC 7/7] ARM: dts: sun9i: Add secure SRAM node used for MCPM SMP hotplug Chen-Yu Tsai
2015-05-20 10:08 ` Maxime Ripard
2015-05-24 15:55 ` [linux-sunxi] " Chen-Yu Tsai
2015-05-25 21:24 ` Maxime Ripard
2015-05-26 16:47 ` Chen-Yu Tsai
2015-06-11 16:33 ` Maxime Ripard
2015-05-16 10:08 ` [linux-sunxi] [RFC 0/7] ARM: sun9i: SMP support with Multi-Cluster Power Management Ian Campbell
2015-05-17 14:38 ` Maxime Ripard
2015-05-18 5:19 ` Nicolas Pitre
2015-05-18 9:04 ` Maxime Ripard
2015-05-19 2:51 ` Chen-Yu Tsai
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