From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755832AbbESJmX (ORCPT ); Tue, 19 May 2015 05:42:23 -0400 Received: from mail-bn1on0139.outbound.protection.outlook.com ([157.56.110.139]:18832 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1755781AbbESJmR (ORCPT ); Tue, 19 May 2015 05:42:17 -0400 X-Greylist: delayed 5102 seconds by postgrey-1.27 at vger.kernel.org; Tue, 19 May 2015 05:42:17 EDT Authentication-Results: spf=none (sender IP is 165.204.84.222) smtp.mailfrom=amd.com; alien8.de; dkim=none (message not signed) header.d=none; X-WSS-ID: 0NOLCAC-08-06B-02 X-M-MSG: Date: Tue, 19 May 2015 17:42:54 +0800 From: Huang Rui To: Borislav Petkov CC: Len Brown , "Rafael J. Wysocki" , "linux-kernel@vger.kernel.org" , Fengguang Wu , Aaron Lu , "Li, Tony" , Thomas Gleixner Subject: Re: Mwait usage on AMD processors Message-ID: <20150519094253.GA11328@hr-slim.amd.com> References: <20150514065451.GA29830@hr-slim.amd.com> <20150514092137.GA29235@pd.tnic> <20150514101727.GA6552@hr-slim.amd.com> <20150514112303.GC29125@pd.tnic> <20150514133857.GB6552@hr-slim.amd.com> <20150514142051.GD29125@pd.tnic> <20150519072552.GA28547@hr-slim.amd.com> <20150519085017.GA4641@pd.tnic> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20150519085017.GA4641@pd.tnic> User-Agent: Mutt/1.5.21 (2010-09-15) X-EOPAttributedMessage: 0 X-Microsoft-Exchange-Diagnostics: 1;BL2FFO11OLC003;1:NgXmgF3npIBnU8+tkMSqFwkN8ZVgeNLEVVoxb4cSZ8lY94F3Gll4sLkdGCvS2dld9I9erIHUpZuAL4cRABYYxFYOVZMSNTqeHDMjYIR5T4gh1Hdxno0wsuqjpRbQYDLJTQMRSySg7IpzO8tS8bkXPmShouiaFnv+7wh9vdqNyLQAAtIggVh1eKqxQ9/Znc5ZPEEHJFASv0EIYhB6lxCyRzMOLRHRAuJmShQnKX8Bbn9cFH+k74jQQX2XXHwXdl9WNzP2dZBahOCe/3Sc5rcd8yqg5L4Q0RR1pMYgRO/iB58= X-Forefront-Antispam-Report: CIP:165.204.84.222;CTRY:US;IPV:NLI;EFV:NLI;SFV:NSPM;SFS:(10019020)(6009001)(428002)(164054003)(189002)(24454002)(51704005)(199003)(189998001)(46406003)(87936001)(33656002)(5001830100001)(5001860100001)(83506001)(105586002)(93886004)(110136002)(23726002)(50466002)(77096005)(68736005)(77156002)(62966003)(92566002)(2950100001)(97756001)(86362001)(106466001)(46102003)(53416004)(4001350100001)(4001540100001)(97736004)(47776003)(64706001)(54356999)(50986999)(76176999)(101416001);DIR:OUT;SFP:1102;SCL:1;SRVR:CO1PR02MB078;H:atltwp02.amd.com;FPR:;SPF:None;PTR:InfoDomainNonexistent;MX:1;A:1;LANG:en; X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:CO1PR02MB078; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(601004)(5005006)(3002001);SRVR:CO1PR02MB078;BCL:0;PCL:0;RULEID:;SRVR:CO1PR02MB078; X-Forefront-PRVS: 0581B5AB35 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 May 2015 09:42:13.2068 (UTC) X-MS-Exchange-CrossTenant-Id: fde4dada-be84-483f-92cc-e026cbee8e96 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=fde4dada-be84-483f-92cc-e026cbee8e96;Ip=[165.204.84.222];Helo=[atltwp02.amd.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO1PR02MB078 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, May 19, 2015 at 04:50:17PM +0800, Borislav Petkov wrote: > On Tue, May 19, 2015 at 03:25:53PM +0800, Huang Rui wrote: > > Apology that cause to misunderstand. It's not as same as intel. > > Intel is able to go to C1E like you said, the C1E has less power > > consumption than C1 on Intel platform. > > You still misunderstand - I'm not talking about Intel platforms here but > AMD ones. On AMD we never enter idle with MWAIT - we do HLT which enters > C1 and then the hw enters C1E when a bunch of conditions are fulfilled. > OK, got it. I see on AMD platforms, we all use default_idle (HLT). > > The faster waiting exit speed. But it's hard to test the improvement, > > do you have any idea? It's told by HW designer. > > You can test the improvement with a special setup only. Unless you can > read out power consumption of a box while it is idle. > Could you please explain how to create the "special setup"? Actually, that's my difficulty. > The exit-idle speed only does not suffice to switch to MWAIT though, > IMHO. I think power consumption in idle should be the relevant metric > here. > Yes, I agree with you. So that's why I was asking to provide an optional parameter, not set it default. > > Current CPU, power consumption cannot go to deeper low power state > > (C1) via mwaitx/mwait. But HW designers will implement it in future > > processors. > > So future CPUs we will switch to MWAIT. I don't see a problem with that. > Yes, at that time, we would like to use mwaitx/mwait as default idle routine for AMD. Thanks, Rui