From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753837AbbFIRaV (ORCPT ); Tue, 9 Jun 2015 13:30:21 -0400 Received: from mezzanine.sirena.org.uk ([106.187.55.193]:50594 "EHLO mezzanine.sirena.org.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752213AbbFIRaO (ORCPT ); Tue, 9 Jun 2015 13:30:14 -0400 Date: Tue, 9 Jun 2015 18:30:04 +0100 From: Mark Brown To: Cyrille Pitchen Cc: nicolas.ferre@atmel.com, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org Message-ID: <20150609173004.GO14071@sirena.org.uk> References: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="+aOZGdcGYL8FotQd" Content-Disposition: inline In-Reply-To: X-Cookie: The end of labor is to gain leisure. User-Agent: Mutt/1.5.23 (2014-03-12) X-SA-Exim-Connect-IP: 94.175.94.161 X-SA-Exim-Mail-From: broonie@sirena.org.uk Subject: Re: [PATCH v3 3/3] spi: atmel: add support to FIFOs X-SA-Exim-Version: 4.2.1 (built Mon, 26 Dec 2011 16:24:06 +0000) X-SA-Exim-Scanned: Yes (on mezzanine.sirena.org.uk) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --+aOZGdcGYL8FotQd Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, Jun 09, 2015 at 01:53:54PM +0200, Cyrille Pitchen wrote: > To enable the FIFO feature a "atmel,fifo-size" attribute with a strictly > positive value must be added into the node of the device-tree describing > the spi controller. I'd expect the driver to use FIFOs any time they make sense, I wouldn't expect this to be something that requires configuration - I'd expect that there's going to be at least some FIFO in all versions of the IP, even if the size varies. Is that not the case? > When FIFOs are enabled, the RX one is forced to operate in SINGLE data > mode because this driver configures the spi controller as a master. In > master mode only, the Received Data Register has an additionnal Peripheral > Chip Select field, which prevents us from reading more than a single data > at each register access. >=20 > Besides, the TX FIFO operates in MULTIPLE data mode. However, even when a This is very hard to understand as I have no idea what single and multiple data modes are, sorry. Please write your commit messages so they can be read by people who aren't familiar with the internals of the IP. --+aOZGdcGYL8FotQd Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQEcBAEBCAAGBQJVdyKcAAoJECTWi3JdVIfQK0UH/26wVok4vSoxLx+X576KU4cH tdNWK/GNQVxiHH9k46jXMJ2oN+rh8hpJGpIZKw9Lcjqor2jP1pSOfcFcQJIhCkBu uiGEUBb/AwcQNCuwyhg47flYqRZUiq4w+dkbx2GLOvOkXIIw7DmSRq522hHk7Qqo Lb8BoJha1T8Tjk28vd0KuzeosjRDYvVEiTafkzSbvJWUekJlHo4hZN8JpwILyIlG RjX9sSJYHX0I3Gdyjn7pheTGaZ0NQBLI3+93+lgzzx+2mCciYyVn4C4D5XH80O5G fP3h93prWSjYZRnD9ErrMHjbxifT9QJPawHByEe+cjspyAf3Qla7r5ApcrXmgaY= =jnsy -----END PGP SIGNATURE----- --+aOZGdcGYL8FotQd--