From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756654AbbGTI4M (ORCPT ); Mon, 20 Jul 2015 04:56:12 -0400 Received: from e06smtp11.uk.ibm.com ([195.75.94.107]:43815 "EHLO e06smtp11.uk.ibm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756622AbbGTI4I (ORCPT ); Mon, 20 Jul 2015 04:56:08 -0400 X-Helo: d06dlp02.portsmouth.uk.ibm.com X-MailFrom: schwidefsky@de.ibm.com X-RcptTo: linux-kernel@vger.kernel.org Date: Mon, 20 Jul 2015 10:56:00 +0200 From: Martin Schwidefsky To: Ingo Molnar Cc: Heiko Carstens , Linus Torvalds , linux-kernel@vger.kernel.org, Thomas Gleixner , "H. Peter Anvin" , Andy Lutomirski , Dave Hansen , Andrew Morton , Oleg Nesterov Subject: Re: [PATCH] sched, s390: Fix the fallout of increasing the offset of 'thread_struct' within 'task_struct' Message-ID: <20150720105600.79b10fe4@mschwide> In-Reply-To: <20150720083847.GC12468@gmail.com> References: <20150718031810.GA19818@gmail.com> <20150720072037.GA3607@osiris> <20150720080032.GA12468@gmail.com> <20150720101219.79fb06bd@mschwide> <20150720083847.GC12468@gmail.com> X-Mailer: Claws Mail 3.9.3 (GTK+ 2.24.23; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 15072008-0041-0000-0000-0000052487CF Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 20 Jul 2015 10:38:47 +0200 Ingo Molnar wrote: > > * Martin Schwidefsky wrote: > > > diff --git a/arch/s390/kernel/entry.S b/arch/s390/kernel/entry.S > > index 3238893..84062e7 100644 > > --- a/arch/s390/kernel/entry.S > > +++ b/arch/s390/kernel/entry.S > > @@ -178,17 +178,21 @@ _PIF_WORK = (_PIF_PER_TRAP) > > */ > > ENTRY(__switch_to) > > stmg %r6,%r15,__SF_GPRS(%r15) # store gprs of prev task > > - stg %r15,__THREAD_ksp(%r2) # store kernel stack of prev > > - lg %r4,__THREAD_info(%r2) # get thread_info of prev > > - lg %r5,__THREAD_info(%r3) # get thread_info of next > > + lgr %r1,%r2 > > + aghi %r1,__TASK_thread # thread_struct of prev task > > + lg %r4,__TASK_thread_info(%r2) # get thread_info of prev > > + lg %r5,__TASK_thread_info(%r3) # get thread_info of next > > + stg %r15,__THREAD_ksp(%r1) # store kernel stack of prev > > + lgr %r1,%r3 > > + aghi %r1,__TASK_thread # thread_struct of next task > > lgr %r15,%r5 > > aghi %r15,STACK_INIT # end of kernel stack of next > > stg %r3,__LC_CURRENT # store task struct of next > > stg %r5,__LC_THREAD_INFO # store thread info of next > > stg %r15,__LC_KERNEL_STACK # store end of kernel stack > > + lg %r15,__THREAD_ksp(%r1) # load kernel stack of next > > lctl %c4,%c4,__TASK_pid(%r3) # load pid to control reg. 4 > > mvc __LC_CURRENT_PID+4(4,%r0),__TASK_pid(%r3) # store pid of next > > - lg %r15,__THREAD_ksp(%r3) # load kernel stack of next > > lmg %r6,%r15,__SF_GPRS(%r15) # load gprs of next task > > br %r14 > > Btw., I think we'd be slightly better off with the variant I sent: that way the > offset arithmetics are done in C code and are ready in the relevant registers by > the time they are used in __switch_to(). If we save any instruction then not many, we are trading additional parameter passing vs. four additional instructions in __switch_to. With this variant the fallout is kept at a minimum which I would prefer at this point. > > > > @@ -417,6 +421,7 @@ ENTRY(pgm_check_handler) > > LAST_BREAK %r14 > > lg %r15,__LC_KERNEL_STACK > > lg %r14,__TI_task(%r12) > > + aghi %r14,__TASK_thread # pointer to thread_struct > > lghi %r13,__LC_PGM_TDB > > tm __LC_PGM_ILC+2,0x02 # check for transaction abort > > jz 2f > > Don't we also need the chunk I have: > > @@ -448,6 +449,7 @@ ENTRY(pgm_check_handler) > nill %r10,0x007f > sll %r10,2 > je .Lsysc_return > + ahi %r14,-__TASK_thread_struct # r14 now points to 'current' > lgf %r1,0(%r10,%r1) # load address of handler routine > lgr %r2,%r11 # pass pointer to pt_regs > basr %r14,%r1 # branch to interrupt-handler > > Because the 'basr' line relies on 'r14' having task_struct, I think? > > But I don't really know what I'm talking about here ... The basr instruction is one of the function calling instructions and %r14 is used for the return address. Between function calls the register is basically free. So far it is used for the task_struct pointer (the code following the "lg %r14,__TI_task(%r12)"). What I noticed is that the pointer is only used to access the embedded thread_struct. To get from the task_struct to a thread_struct a single aghi is needed. The rest is moving stuff around in asm-offsets.c -- blue skies, Martin. "Reality continues to ruin my life." - Calvin.