From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752654AbbIOPe6 (ORCPT ); Tue, 15 Sep 2015 11:34:58 -0400 Received: from e38.co.us.ibm.com ([32.97.110.159]:44688 "EHLO e38.co.us.ibm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751797AbbIOPe4 (ORCPT ); Tue, 15 Sep 2015 11:34:56 -0400 X-Helo: d03dlp03.boulder.ibm.com X-MailFrom: paulmck@linux.vnet.ibm.com X-RcptTo: linux-kernel@vger.kernel.org Date: Tue, 15 Sep 2015 08:34:48 -0700 From: "Paul E. McKenney" To: Peter Zijlstra Cc: Davidlohr Bueso , Ingo Molnar , Thomas Gleixner , linux-kernel@vger.kernel.org, Davidlohr Bueso Subject: Re: [PATCH -tip 2/3] sched/wake_q: Relax to acquire semantics Message-ID: <20150915153448.GI4029@linux.vnet.ibm.com> Reply-To: paulmck@linux.vnet.ibm.com References: <1442216244-4409-1-git-send-email-dave@stgolabs.net> <1442216244-4409-2-git-send-email-dave@stgolabs.net> <20150914123241.GR18489@twins.programming.kicks-ass.net> <20150914210806.GG19736@linux-q0g1.site> <20150915094949.GA16853@twins.programming.kicks-ass.net> <20150915095512.GA18673@twins.programming.kicks-ass.net> <20150915124142.GF4029@linux.vnet.ibm.com> <20150915124800.GB16853@twins.programming.kicks-ass.net> <20150915140922.GG4029@linux.vnet.ibm.com> <20150915141439.GE16853@twins.programming.kicks-ass.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20150915141439.GE16853@twins.programming.kicks-ass.net> User-Agent: Mutt/1.5.21 (2010-09-15) X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 15091515-0029-0000-0000-00000CA0F31D Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Sep 15, 2015 at 04:14:39PM +0200, Peter Zijlstra wrote: > On Tue, Sep 15, 2015 at 07:09:22AM -0700, Paul E. McKenney wrote: > > On Tue, Sep 15, 2015 at 02:48:00PM +0200, Peter Zijlstra wrote: > > > On Tue, Sep 15, 2015 at 05:41:42AM -0700, Paul E. McKenney wrote: > > > > > Never mind, the PPC people will implement this with lwsync and that is > > > > > very much not transitive IIRC. > > > > > > > > I am probably lost on context, but... > > > > > > > > It turns out that lwsync is transitive in special cases. One of them > > > > is a series of release-acquire pairs, which can extend indefinitely. > > > > > > > > Does that help in this case? > > > > > > Probably not, but good to know. I still don't think we want to rely on > > > ACQUIRE/RELEASE being transitive in general though. > > > > OK, I will bite... Why not? > > It would mean us reviewing all archs (again) and documenting it I > suppose. Which is of course entirely possible. > > That said, I don't think the case at hand requires it, so lets postpone > this for now ;-) True enough, but in my experience smp_store_release() and smp_load_acquire() are a -lot- easier to use than other barriers, and transitivity will help promote their use. So... All the TSO architectures (x86, s390, SPARC, HPPA, ...) support transitive smp_store_release()/smp_load_acquire() via their native ordering in combination with barrier() macros. x86 with CONFIG_X86_PPRO_FENCE=y, which is not TSO, uses an mfence instruction. Power supports this via lwsync's partial cumulativity. ARM64 supports it in SMP via the new ldar and stlr instructions (in non-SMP, it uses barrier(), which suffices in that case). IA64 supports this via total ordering of all release instructions in theory and by the actual full-barrier implementation in practice (and the fact that gcc emits st.rel and ld.acq instructions for volatile stores and loads). All other architectures use smp_mb(), which is transitive. Did I miss anything? Thanx, Paul