From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756162AbbIVOLj (ORCPT ); Tue, 22 Sep 2015 10:11:39 -0400 Received: from eusmtp01.atmel.com ([212.144.249.243]:52108 "EHLO eusmtp01.atmel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751112AbbIVOLh (ORCPT ); Tue, 22 Sep 2015 10:11:37 -0400 Date: Tue, 22 Sep 2015 16:07:03 +0200 From: Ludovic Desroches To: Thomas Gleixner CC: Boris Brezillon , Ludovic Desroches , , , , , , , , Subject: Re: [PATCH 1/3] irqchip: atmel-aic5: fix bug with mask/unmask Message-ID: <20150922140703.GC28781@odux.rfo.atmel.com> Mail-Followup-To: Thomas Gleixner , Boris Brezillon , jason@lakedaemon.net, marc.zyngier@arm.com, linux-kernel@vger.kernel.org, sasha.levin@oracle.com, linux-arm-kernel@lists.infradead.org, nicolas.ferre@atmel.com, alexandre.belloni@free-electrons.com, Wenyou.Yang@atmel.com References: <1442843173-2390-1-git-send-email-ludovic.desroches@atmel.com> <20150922135558.7be8ac1c@bbrezillon> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Sep 22, 2015 at 03:50:30PM +0200, Thomas Gleixner wrote: > On Tue, 22 Sep 2015, Boris Brezillon wrote: > > On Tue, 22 Sep 2015 12:27:08 +0200 (CEST) > > Thomas Gleixner wrote: > > > Why is this locking dgc->gc[0] and fiddling with some other generic > > > chip? > > > > Actually, we always access the same set of registers for all irqs of the > > domain, and thus need to take the same lock (I chose the one contained > > in the first generic irqchip, but I guess it could work with the others > > too, as long as we always take the same one) before accessing them > > because the configuration is done in two steps: > > > > 1/ specify the irq line you want to configure > > 2/ set the new configuration > > > > Regarding register accesses, all generic chips are configured to > > point to the same registers, so accessing them from the 'base' generic > > chip or from the generic chip attached to the irq_data struct is the > > same, though I agree that using bgc would add some consistency to the > > implementation. > > Fair enough. It just deserves a comment for the casual reader. > Thanks for the addition of the comment. Ludovic