From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934166AbbJHPRe (ORCPT ); Thu, 8 Oct 2015 11:17:34 -0400 Received: from mail-lb0-f173.google.com ([209.85.217.173]:32877 "EHLO mail-lb0-f173.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933786AbbJHPRd (ORCPT ); Thu, 8 Oct 2015 11:17:33 -0400 Date: Thu, 8 Oct 2015 17:17:46 +0200 From: Christoffer Dall To: "Suzuki K. Poulose" Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Catalin.Marinas@arm.com, Will.Deacon@arm.com, Mark.Rutland@arm.com, Marc.Zyngier@arm.com, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, ard.biesheuvel@linaro.org Subject: Re: [PATCH 10/15] arm64: kvm: Fix {V}TCR_EL2_TG0 mask Message-ID: <20151008151746.GE20936@cbox> References: <1442331684-28818-1-git-send-email-suzuki.poulose@arm.com> <1442331684-28818-11-git-send-email-suzuki.poulose@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1442331684-28818-11-git-send-email-suzuki.poulose@arm.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Sep 15, 2015 at 04:41:19PM +0100, Suzuki K. Poulose wrote: > From: "Suzuki K. Poulose" > > {V}TCR_EL2_TG0 is a 2bit wide field, where: > > 00 - 4K > 01 - 64K > 10 - 16K > > But we use only 1 bit, which has worked well so far since > we never cared about 16K. Fix it for 16K support. > > Cc: Catalin Marinas > Cc: Will Deacon > Cc: Marc Zyngier > Cc: Christoffer Dall > Cc: kvmarm@lists.cs.columbia.edu > Acked-by: Mark Rutland > Signed-off-by: Suzuki K. Poulose > --- > arch/arm64/include/asm/kvm_arm.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h > index 7605e09..bdf139e 100644 > --- a/arch/arm64/include/asm/kvm_arm.h > +++ b/arch/arm64/include/asm/kvm_arm.h > @@ -98,7 +98,7 @@ > #define TCR_EL2_TBI (1 << 20) > #define TCR_EL2_PS (7 << 16) > #define TCR_EL2_PS_40B (2 << 16) > -#define TCR_EL2_TG0 (1 << 14) > +#define TCR_EL2_TG0 (3 << 14) > #define TCR_EL2_SH0 (3 << 12) > #define TCR_EL2_ORGN0 (3 << 10) > #define TCR_EL2_IRGN0 (3 << 8) > @@ -110,7 +110,7 @@ > > /* VTCR_EL2 Registers bits */ > #define VTCR_EL2_PS_MASK (7 << 16) > -#define VTCR_EL2_TG0_MASK (1 << 14) > +#define VTCR_EL2_TG0_MASK (3 << 14) > #define VTCR_EL2_TG0_4K (0 << 14) > #define VTCR_EL2_TG0_64K (1 << 14) > #define VTCR_EL2_SH0_MASK (3 << 12) > -- > 1.7.9.5 > Reviewed-by: Christoffer Dall