From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752552AbbJJRWA (ORCPT ); Sat, 10 Oct 2015 13:22:00 -0400 Received: from mail-lb0-f169.google.com ([209.85.217.169]:34735 "EHLO mail-lb0-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752154AbbJJRV6 (ORCPT ); Sat, 10 Oct 2015 13:21:58 -0400 Date: Sat, 10 Oct 2015 19:22:14 +0200 From: Christoffer Dall To: "Suzuki K. Poulose" Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Catalin.Marinas@arm.com, Will.Deacon@arm.com, Mark.Rutland@arm.com, Marc.Zyngier@arm.com, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, ard.biesheuvel@linaro.org Subject: Re: [PATCH 11/15] arm64: Cleanup VTCR_EL2 computation Message-ID: <20151010172214.GJ29128@cbox> References: <1442331684-28818-1-git-send-email-suzuki.poulose@arm.com> <1442331684-28818-12-git-send-email-suzuki.poulose@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1442331684-28818-12-git-send-email-suzuki.poulose@arm.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Sep 15, 2015 at 04:41:20PM +0100, Suzuki K. Poulose wrote: > From: "Suzuki K. Poulose" > > No functional changes. Group the common bits for VCTR_EL2 > initialisation for better readability. The granule size > and the entry level are controlled by the page size. > > Cc: Christoffer Dall > Cc: Marc Zyngier > Cc: kvmarm@lists.cs.columbia.edu > Signed-off-by: Suzuki K. Poulose > --- > arch/arm64/include/asm/kvm_arm.h | 13 +++++++------ > 1 file changed, 7 insertions(+), 6 deletions(-) > > diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h > index bdf139e..699554d 100644 > --- a/arch/arm64/include/asm/kvm_arm.h > +++ b/arch/arm64/include/asm/kvm_arm.h > @@ -138,6 +138,9 @@ > * The magic numbers used for VTTBR_X in this patch can be found in Tables > * D4-23 and D4-25 in ARM DDI 0487A.b. > */ > +#define VTCR_EL2_COMMON_BITS (VTCR_EL2_SH0_INNER | VTCR_EL2_ORGN0_WBWA | \ > + VTCR_EL2_IRGN0_WBWA | VTCR_EL2_T0SZ_40B) > + > #ifdef CONFIG_ARM64_64K_PAGES > /* > * Stage2 translation configuration: > @@ -145,9 +148,8 @@ > * 64kB pages (TG0 = 1) > * 2 level page tables (SL = 1) > */ > -#define VTCR_EL2_FLAGS (VTCR_EL2_TG0_64K | VTCR_EL2_SH0_INNER | \ > - VTCR_EL2_ORGN0_WBWA | VTCR_EL2_IRGN0_WBWA | \ > - VTCR_EL2_SL0_LVL1 | VTCR_EL2_T0SZ_40B) > +#define VTCR_EL2_FLAGS (VTCR_EL2_TG0_64K | VTCR_EL2_SL0_LVL1 | \ > + VTCR_EL2_COMMON_BITS) > #define VTTBR_X (38 - VTCR_EL2_T0SZ_40B) > #else > /* > @@ -156,9 +158,8 @@ > * 4kB pages (TG0 = 0) > * 3 level page tables (SL = 1) > */ > -#define VTCR_EL2_FLAGS (VTCR_EL2_TG0_4K | VTCR_EL2_SH0_INNER | \ > - VTCR_EL2_ORGN0_WBWA | VTCR_EL2_IRGN0_WBWA | \ > - VTCR_EL2_SL0_LVL1 | VTCR_EL2_T0SZ_40B) > +#define VTCR_EL2_FLAGS (VTCR_EL2_TG0_4K | VTCR_EL2_SL0_LVL1 | \ > + VTCR_EL2_COMMON_BITS) > #define VTTBR_X (37 - VTCR_EL2_T0SZ_40B) > #endif > > -- > 1.7.9.5 > Reviewed-by: Christoffer Dall