Re: [PATCH 1/4] x86, perf: Use a new PMU ack sequence on Skylake

From: Peter Zijlstra <peterz@infradead.org>
To: Andi Kleen <andi@firstfloor.org>
Cc: linux-kernel@vger.kernel.org, Andi Kleen <ak@linux.intel.com>,
	Ingo Molnar <mingo@kernel.org>,
	Thomas Gleixner <tglx@linutronix.de>
Subject: Re: [PATCH 1/4] x86, perf: Use a new PMU ack sequence on Skylake
Date: Fri, 16 Oct 2015 13:51:07 +0200	[thread overview]
Message-ID: <20151016115107.GV3816@twins.programming.kicks-ass.net> (raw)
In-Reply-To: <1444952280-24184-2-git-send-email-andi@firstfloor.org>

On Thu, Oct 15, 2015 at 04:37:57PM -0700, Andi Kleen wrote:

> One side effect is that the old retry loop is not possible anymore,
> as the counters stay unacked for the majority of the PMI handler,
> but that is not a big loss, as "profiling" the PMI was always
> a bit dubious. For the old ack sequence it is still supported.

Its not a self profiling thing, its a safety feature. The interrupt very
explicitly disables all PMU counters, which would make self profiling
impossible.

And note that the "perfevents: irq loop stuck!" WARN is still
triggerable on my IVB (although I've not managed to find the root cause
of that).

What would happen with a 'stuck' event in the new scheme?

> In principle the sequence should work on other CPUs too, but
> since I only tested on Skylake it is only enabled there.

I would very much like a reduction of the ack states. You introduced the
late thing, which should also work for everyone, and now you introduce
yet another variant.

I would very much prefer a single ack scheme if at all possible.