From: Peter Zijlstra <peterz@infradead.org>
To: Andi Kleen <ak@linux.intel.com>
Cc: Andi Kleen <andi@firstfloor.org>,
linux-kernel@vger.kernel.org, Ingo Molnar <mingo@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
Mike Galbraith <umgwanakikbuti@gmail.com>
Subject: Re: [PATCH 1/4] x86, perf: Use a new PMU ack sequence on Skylake
Date: Fri, 16 Oct 2015 17:00:35 +0200 [thread overview]
Message-ID: <20151016150035.GY3816@twins.programming.kicks-ass.net> (raw)
In-Reply-To: <20151016133514.GB15102@tassilo.jf.intel.com>
On Fri, Oct 16, 2015 at 06:35:14AM -0700, Andi Kleen wrote:
> > > In principle the sequence should work on other CPUs too, but
> > > since I only tested on Skylake it is only enabled there.
> >
> > I would very much like a reduction of the ack states. You introduced the
> > late thing, which should also work for everyone, and now you introduce
> > yet another variant.
>
> Ingo suggested to do it this way. Originally I thought it wasn't needed,
> but I think now that late-ack made some of the races that eventually
> caused Skylake LBR to fall over worse. So in hindsight it was a good idea
> to not use it everywhere.
>
> > I would very much prefer a single ack scheme if at all possible.
>
> Could enable it everywhere, but then users would need to test it
> on most types of CPUs, as I can't.
I think Mike still has a Core2 machine (and I might be able to dig out a
laptop), Ingo should have a NHM(-EP), I have SNB, IVB-EP, HSW. So if you
could test at least BDW and SKL we might have decent test coverage.
Ingo, do you want to first merge the safe patch and then clean up?
next prev parent reply other threads:[~2015-10-16 15:00 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-15 23:37 perf: Some improvements for Skylake perf Andi Kleen
2015-10-15 23:37 ` [PATCH 1/4] x86, perf: Use a new PMU ack sequence on Skylake Andi Kleen
2015-10-16 11:51 ` Peter Zijlstra
2015-10-16 13:35 ` Andi Kleen
2015-10-16 15:00 ` Peter Zijlstra [this message]
2015-10-16 16:14 ` Mike Galbraith
2015-10-19 7:08 ` Ingo Molnar
2015-10-15 23:37 ` [PATCH 2/4] x86, perf: Factor out BTS enable/disable functions Andi Kleen
2015-10-15 23:37 ` [PATCH 3/4] perf, x86: Use counter freezing with Arch Perfmon v4 Andi Kleen
2015-10-15 23:38 ` [PATCH 4/4] x86, perf: Use INST_RETIRED.PREC_DIST for cycles:pp on Skylake Andi Kleen
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20151016150035.GY3816@twins.programming.kicks-ass.net \
--to=peterz@infradead.org \
--cc=ak@linux.intel.com \
--cc=andi@firstfloor.org \
--cc=linux-kernel@vger.kernel.org \
--cc=mingo@kernel.org \
--cc=tglx@linutronix.de \
--cc=umgwanakikbuti@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).