From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756942AbbJVIrm (ORCPT ); Thu, 22 Oct 2015 04:47:42 -0400 Received: from down.free-electrons.com ([37.187.137.238]:37418 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1756837AbbJVIrh (ORCPT ); Thu, 22 Oct 2015 04:47:37 -0400 Date: Thu, 22 Oct 2015 10:47:35 +0200 From: Maxime Ripard To: Jean-Francois Moine Cc: Jens Kuske , devicetree@vger.kernel.org, Vishnu Patekar , Emilio =?iso-8859-1?Q?L=F3pez?= , Michael Turquette , linux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org, Hans de Goede , Chen-Yu Tsai , Rob Herring , Philipp Zabel , Linus Walleij , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI Message-ID: <20151022084735.GR10947@lukather> References: <1445444428-4652-1-git-send-email-jenskuske@gmail.com> <1445444428-4652-2-git-send-email-jenskuske@gmail.com> <20151022080508.GN10947@lukather> <20151022102959.09f0a1f4@OPI2> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="phbq2bkSb+hZnunM" Content-Disposition: inline In-Reply-To: <20151022102959.09f0a1f4@OPI2> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --phbq2bkSb+hZnunM Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Oct 22, 2015 at 10:29:59AM +0200, Jean-Francois Moine wrote: > On Thu, 22 Oct 2015 10:05:08 +0200 > Maxime Ripard wrote: >=20 > > > + uart0: serial@01c28000 { > > > + compatible =3D "snps,dw-apb-uart"; > > > + reg =3D <0x01c28000 0x400>; > > > + interrupts =3D ; > > > + reg-shift =3D <2>; > > > + reg-io-width =3D <4>; > > > + clocks =3D <&bus_gates 112>; > > > + resets =3D <&bus_rst 208>; =20 > >=20 > > It's a bit weird that the clocks and reset indices don't match, > > usually they do. > >=20 > > What's even weirder is that there's a 96 offset between the two (4 * > > 32), is this expected? >=20 > Yes, this is conform to the H3 documentation. Not really. The uart0 reset is the bit 16, in the reset register 4. 4 * 32 + 16 =3D 44. Not 112, but still not 208 either. Maxime --=20 Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com --phbq2bkSb+hZnunM Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBAgAGBQJWKKKnAAoJEBx+YmzsjxAg0jYQAI97LL/VMs1vaTU68vKseuci L8jiZSfXxrr+X8AFoLfNHh6SiSEy9/3qO3oIARBKZnnvShajlAHtkVoKdlMgY2CW SICKNW0GTO2U5p7bKANk/mKKeKMWFiM8T8SWe9+NkyMaILXLNtp/ff5PDEqvSrgx N13YkMkVGJH1ERv9g8TtZkEoupAqVbHRvjkgF5XKt0i219o/ABfGpe/+YeIl3psS pGjAyIzsni+oR1FoYcagtHNT9koZTq/Vafl/CdIUVxdMKLAueQ822gVSP3HjdnTq AcTzkTemZ1FqB6RlXhJcxptTyPGyQ+TMRrsOz1jBCYL66ORoXrRt/KxcEC951P6r cEamF7kAdfxrZyX3NKRL1QDYyMmcmm7ckCw/Dn9AiQLJUOz2Q5J85VaR0gBRjSsL Qn8loc8vA+iH7688gPBcdECT7+FTwwqLn+feFmSDQb/HHcMoRiNOilGTNQiWxoQP LaoxGsAxQPv23dQhNA1K3An6ByWOCyKoShusEJdzdVg/2dcIXXWCtKgu7N+eirKT orKPxkjwZTtFhbCfKx3WM2zMfNNeySdsbyBy+lM7PeCfaraRBsfTAiTO00prIpQ6 U9EXQYSPku1DguTD8JKWPocfsfOZmGgn7IJppciP+atBXbMS2LmDg3HgIXHzKpLs IgmzatnHi6fkRmQJNpau =IkSM -----END PGP SIGNATURE----- --phbq2bkSb+hZnunM--