From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965237AbbJVPcI (ORCPT ); Thu, 22 Oct 2015 11:32:08 -0400 Received: from eu-smtp-delivery-143.mimecast.com ([207.82.80.143]:52873 "EHLO eu-smtp-delivery-143.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756368AbbJVPcG convert rfc822-to-8bit (ORCPT ); Thu, 22 Oct 2015 11:32:06 -0400 Date: Thu, 22 Oct 2015 16:32:01 +0100 From: Catalin Marinas To: "Suzuki K. Poulose" Cc: Stephen Rothwell , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , Peter Zijlstra , linux-next@vger.kernel.org, linux-kernel@vger.kernel.org, Marc Zyngier Subject: Re: linux-next: manual merge of the tip tree with the arm64 tree Message-ID: <20151022153201.GD26603@e104818-lin.cambridge.arm.com> References: <20151022132652.611ec628@canb.auug.org.au> <20151022120602.GB28575@e106634-lin.cambridge.arm.com> MIME-Version: 1.0 In-Reply-To: <20151022120602.GB28575@e106634-lin.cambridge.arm.com> User-Agent: Mutt/1.5.23 (2014-03-12) X-OriginalArrivalTime: 22 Oct 2015 15:32:01.0670 (UTC) FILETIME=[CC15AA60:01D10CDE] X-MC-Unique: mKnXBwsHQeaEmRqHtSZg0A-1 Content-Type: text/plain; charset=WINDOWS-1252 Content-Transfer-Encoding: 8BIT Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Oct 22, 2015 at 01:06:03PM +0100, Suzuki K. Poulose wrote: > On Thu, Oct 22, 2015 at 01:26:52PM +1100, Stephen Rothwell wrote: > > Today's linux-next merge of the tip tree got a conflict in: > > > > arch/arm64/kernel/cpufeature.c > > > > between commit: > > > > da8d02d19ffd ("arm64/capabilities: Make use of system wide safe value") > > > > from the arm64 tree and commit: > > > > 963fcd409587 ("arm64: cpufeatures: Check ICC_EL1_SRE.SRE before enabling ARM64_HAS_SYSREG_GIC_CPUIF") > > > > from the tip tree. > > > > I fixed it up (I have no idea here, so I just used the arm64 tree version) > > and can carry the fix as necessary (no action is required). > > We need the following patch applied to fix the conflict correctly > on top of the -next tree. Or, if it's easier, the combined diff resolution for the conflicting code: --------8<---------------------------- diff --cc arch/arm64/kernel/cpufeature.c index d0d607452e1d,305f30dc9e63..ec552cf9e12d --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c [...] + static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry) + { + bool has_sre; + - if (!has_id_aa64pfr0_feature(entry)) ++ if (!has_cpuid_feature(entry)) + return false; + + has_sre = gic_enable_sre(); + if (!has_sre) + pr_warn_once("%s present but disabled by higher exception level\n", + entry->desc); + + return has_sre; + } + static const struct arm64_cpu_capabilities arm64_features[] = { { .desc = "GIC system register CPU interface", .capability = ARM64_HAS_SYSREG_GIC_CPUIF, - .matches = has_cpuid_feature, + .matches = has_useable_gicv3_cpuif, - .field_pos = 24, + .sys_reg = SYS_ID_AA64PFR0_EL1, + .field_pos = ID_AA64PFR0_GIC_SHIFT, .min_field_value = 1, }, #ifdef CONFIG_ARM64_PAN --------8<---------------------------- Thanks. -- Catalin