From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753943AbbJWSOM (ORCPT ); Fri, 23 Oct 2015 14:14:12 -0400 Received: from down.free-electrons.com ([37.187.137.238]:42816 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751017AbbJWSOJ (ORCPT ); Fri, 23 Oct 2015 14:14:09 -0400 Date: Fri, 23 Oct 2015 20:14:06 +0200 From: Maxime Ripard To: Jens Kuske Cc: Chen-Yu Tsai , Michael Turquette , Linus Walleij , Rob Herring , Philipp Zabel , Emilio =?iso-8859-1?Q?L=F3pez?= , Vishnu Patekar , Hans de Goede , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com Subject: Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI Message-ID: <20151023181406.GK10947@lukather> References: <1445444428-4652-1-git-send-email-jenskuske@gmail.com> <1445444428-4652-2-git-send-email-jenskuske@gmail.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="hvDi6/M7gW6JbuLr" Content-Disposition: inline In-Reply-To: <1445444428-4652-2-git-send-email-jenskuske@gmail.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --hvDi6/M7gW6JbuLr Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Oct 21, 2015 at 06:20:27PM +0200, Jens Kuske wrote: > + bus_gates: clk@01c20060 { > + #clock-cells =3D <1>; > + compatible =3D "allwinner,sun8i-h3-bus-gates-clk"; > + reg =3D <0x01c20060 0x14>; > + clock-indices =3D <5>, <6>, <8>, > + <9>, <10>, <13>, > + <14>, <17>, <18>, > + <19>, <20>, > + <21>, <23>, > + <24>, <25>, > + <26>, <27>, > + <28>, <29>, > + <30>, <31>, <32>, > + <35>, <36>, <37>, > + <40>, <41>, <43>, > + <44>, <52>, <53>, > + <54>, <64>, > + <65>, <69>, <72>, > + <76>, <77>, <78>, > + <96>, <97>, <98>, > + <112>, <113>, > + <114>, <115>, <116>, > + <128>, <135>; > + clocks =3D <&ahb1>, <&ahb1>, <&ahb1>, > + <&ahb1>, <&ahb1>, <&ahb1>, > + <&ahb1>, <&ahb2>, <&ahb1>, > + <&ahb1>, <&ahb1>, > + <&ahb1>, <&ahb1>, > + <&ahb1>, <&ahb1>, > + <&ahb1>, <&ahb1>, > + <&ahb1>, <&ahb2>, > + <&ahb2>, <&ahb2>, <&ahb1>, > + <&ahb1>, <&ahb1>, <&ahb1>, > + <&ahb1>, <&ahb1>, <&ahb1>, > + <&ahb1>, <&ahb1>, <&ahb1>, > + <&ahb1>, <&apb1>, > + <&apb1>, <&apb1>, <&apb1>, > + <&apb1>, <&apb1>, <&apb1>, > + <&apb2>, <&apb2>, <&apb2>, > + <&apb2>, <&apb2>, > + <&apb2>, <&apb2>, <&apb2>, > + <&ahb1>, <&ahb1>; This is not really what I had in mind... This IP has 2 parents, and only two parents. The mapping between the IPs should be done in the driver itself, not in the DT where it is very error prone and barely readable. And note that I never have expected you to use clk-simple-gates either. This is a complicated clock, unlike the other we've seen so far, it definitely deserves a driver of its own. Thanks! Maxime --=20 Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com --hvDi6/M7gW6JbuLr Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBAgAGBQJWKnjuAAoJEBx+YmzsjxAgWgEP/2VuBt8XKdfMzD3wgUrLgYiP TgJ0+0SdfdbaApx66IK+fiYkcHMEvi2xkNZiO6kQdeTEg0X6gul+tNKbtoGOjhEl nqGUeKCQavla9RX/CpuwD2ZUmHZDCwb1DxF/5KVfbKO/xTETq94oU0Xi1FPPTtQ/ IY49vdliC0nLx6GdSaPssO4ue9Sk8tfStLySqkD0/Oc7WqIDIR5Se3kx6skmZDci THICPgAU0lLhzjjCe84RxnXBLB/Z/Q1JDlFfVfzP3USaR53hpbwkQBlZct1guWPS PdZKhrrnz1yc67D9yfIKs2aTHzgnVzqZv4e/Z2Drg2lzR1tyYpiAvQgkvZpy34WP jvTW2q4z2aAMpVPcOq1iC31cjms+RgZF7zrjBcN4jiLGDhN9akAOGA13Hh+UVr/k rchXJsgPky3dqkttF9BwmSAWPmgpuQmKVlbsgbbML1u7AJ1wUcGLOUkYSPkPARnN ZnabFcLBFxVDke+TgH5vutTxMZKorXO2Qr5GyQ4daMIw7aaOXoNwLAOWYMxayaR3 Vs4UfICzrrT4lX4Au+giHUBRqTetfLHLQHdaLB6+nGdcFkHTMhqG0ZYMd2HFRap+ Dt8afQauCDbiaP1oB+nh3gRXU6fiW7WxjCqOwVyGYQmriy8ZOxOfqx2x3qyUpHl8 cyBWVR7cysxknow8RH8F =4u5R -----END PGP SIGNATURE----- --hvDi6/M7gW6JbuLr--