From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751682AbbJXHNc (ORCPT ); Sat, 24 Oct 2015 03:13:32 -0400 Received: from down.free-electrons.com ([37.187.137.238]:50503 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751089AbbJXHNa (ORCPT ); Sat, 24 Oct 2015 03:13:30 -0400 Date: Sat, 24 Oct 2015 09:13:28 +0200 From: Maxime Ripard To: Jean-Francois Moine Cc: Jens Kuske , devicetree@vger.kernel.org, Vishnu Patekar , Emilio =?iso-8859-1?Q?L=F3pez?= , Michael Turquette , linux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org, Hans de Goede , Chen-Yu Tsai , Rob Herring , Philipp Zabel , Linus Walleij , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI Message-ID: <20151024071328.GQ10947@lukather> References: <1445444428-4652-1-git-send-email-jenskuske@gmail.com> <1445444428-4652-2-git-send-email-jenskuske@gmail.com> <20151023181406.GK10947@lukather> <20151023212013.50bcbe4a@OPI2> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="zX3fAKQGR/qU2rkc" Content-Disposition: inline In-Reply-To: <20151023212013.50bcbe4a@OPI2> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --zX3fAKQGR/qU2rkc Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, Oct 23, 2015 at 09:20:13PM +0200, Jean-Francois Moine wrote: > On Fri, 23 Oct 2015 20:14:06 +0200 > Maxime Ripard wrote: >=20 > > On Wed, Oct 21, 2015 at 06:20:27PM +0200, Jens Kuske wrote: > > > + bus_gates: clk@01c20060 { > > > + #clock-cells =3D <1>; > > > + compatible =3D "allwinner,sun8i-h3-bus-gates-clk"; > > > + reg =3D <0x01c20060 0x14>; > > > + clock-indices =3D <5>, <6>, <8>, > > > + <9>, <10>, <13>, > > > + <14>, <17>, <18>, > > > + <19>, <20>, > > > + <21>, <23>, > > > + <24>, <25>, > > > + <26>, <27>, > > > + <28>, <29>, > > > + <30>, <31>, <32>, > > > + <35>, <36>, <37>, > > > + <40>, <41>, <43>, > > > + <44>, <52>, <53>, > > > + <54>, <64>, > > > + <65>, <69>, <72>, > > > + <76>, <77>, <78>, > > > + <96>, <97>, <98>, > > > + <112>, <113>, > > > + <114>, <115>, <116>, > > > + <128>, <135>; > > > + clocks =3D <&ahb1>, <&ahb1>, <&ahb1>, > > > + <&ahb1>, <&ahb1>, <&ahb1>, > > > + <&ahb1>, <&ahb2>, <&ahb1>, > > > + <&ahb1>, <&ahb1>, > > > + <&ahb1>, <&ahb1>, > > > + <&ahb1>, <&ahb1>, > > > + <&ahb1>, <&ahb1>, > > > + <&ahb1>, <&ahb2>, > > > + <&ahb2>, <&ahb2>, <&ahb1>, > > > + <&ahb1>, <&ahb1>, <&ahb1>, > > > + <&ahb1>, <&ahb1>, <&ahb1>, > > > + <&ahb1>, <&ahb1>, <&ahb1>, > > > + <&ahb1>, <&apb1>, > > > + <&apb1>, <&apb1>, <&apb1>, > > > + <&apb1>, <&apb1>, <&apb1>, > > > + <&apb2>, <&apb2>, <&apb2>, > > > + <&apb2>, <&apb2>, > > > + <&apb2>, <&apb2>, <&apb2>, > > > + <&ahb1>, <&ahb1>; =20 > >=20 > > This is not really what I had in mind... > >=20 > > This IP has 2 parents, and only two parents. The mapping between the > > IPs should be done in the driver itself, not in the DT where it is > > very error prone and barely readable. > >=20 > > And note that I never have expected you to use clk-simple-gates > > either. This is a complicated clock, unlike the other we've seen so > > far, it definitely deserves a driver of its own. >=20 > It seems that Allwinner puts the gate definitions anywhere in the array > of registers, so, I think that the H3 scheme will not be the last > complicated one, Maybe, but that's the first one. It doesn't prevent us from reusing the driver later if it happens. > and if the parent clocks are in the code instead of in the DT, we > will have more and more code to develop. I never asked that either. > An other way to describe the gates would be to add containers per parent > (with still a small patch in the clk-simple-gates): >=20 > bus_gates: clk@01c20060 { > #clock-cells =3D <1>; > compatible =3D "allwinner,sun8i-h3-bus-gates-clk"; > reg =3D <0x01c20060 0x14>; > ahb1_gates { > clocks =3D <&ahb1>; > clock-indices =3D <5>, <6>, <8>, > <9>, <10>, <13>, > <14>, <18>, > <19>, <20>, > ...; > }; > clock-output-names =3D "ahb1_ce", "ahb1_dma", "ahb1_mmc0", > "ahb1_mmc1", "ahb1_mmc2", "ahb1_nand", > "ahb1_sdram", "ahb1_ts", > "ahb1_hstimer", "ahb1_spi0", > ...; > }; > ahb2_gates { > clocks =3D <&ahb2>; > clock-indices =3D <17>, <29>, > <30>, <31>, <32>, > ...; > clock-output-names =3D "ahb2_gmac", "ahb2_ohic1", > "ahb2_ohic2", "ahb2_ohic3", "ahb1_ve", > ...; > }; > apb1_gates { > ... > }; > apb2_gates { > ... > }; > }; Or simply bus_gates { clocks =3D <&ahb1>, <&ahb2>; clock-indices =3D <5>, <6>, <8>, ... clock-output-names =3D "bus_ce", "bus_dma", "bus_mmc0" }; Maxime --=20 Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com --zX3fAKQGR/qU2rkc Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBAgAGBQJWKy+YAAoJEBx+YmzsjxAgDIwP/iTqF9TxUtREaXpA1c2IQXVr zt+5rFVKbpAn/P0iLhasTWsaRmOztTsiePNoGx/3lVWLZkJVjS0j9QPqBA40xY51 NOnWF8WUggeZbRZHcqB1GJHBRf4V7ZMN1tBfQxJGX0fDPu6HM6r64z3oHC8XT/Oc m/SItBVRw7+Szz9vhzp3Ig1/Ee90UAu0NUIk54TEXCXjtVBKSKd1KHbO89iLipwI l8QC3BbHOOmqfoQxWPNHidK14fxrpSKWZoAa1HBJ/g0V1m2bfR1uUtYLEmuLqROW VLpYhBOprzDEI974ZtDQQA1DOje6Nkj2DlwPz2+2A+BYIAwg9Az/wWHHWJPTkCQ4 kmCr46PmfDa2zVqSEYfmqjv/qs2W299/j5ngDWjyBejV4ESChFzIf94cypgItGQR 8PuLhaQe1Qf9oBnVIOZWsb8FMY553xeh+dw33kSzGvlzRzd9bsf/2Ru+ffqtWat/ Q5y1KIDGusXo6lDd6TljkFC+M/w/r3CJ/wkuwKvv3/l88T6w1HVdr4rQQOekucwM qi1BcF44fe1WyeCP6+6KG+UqdYrsYALK7irMyaChdrY6eeuV20ZVqTBn249RZ8Wk NoNC5e/AqxhK/9QLB7Umb7trIrxACwG0olta7bkXGUKPO/m8DyussH+Bgk4d6UG3 gw9wIieku+j/2vDH6niO =4lZS -----END PGP SIGNATURE----- --zX3fAKQGR/qU2rkc--