From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753611AbbJ0CWa (ORCPT ); Mon, 26 Oct 2015 22:22:30 -0400 Received: from mx0b-0016f401.pphosted.com ([67.231.156.173]:59134 "EHLO mx0b-0016f401.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751704AbbJ0CW2 (ORCPT ); Mon, 26 Oct 2015 22:22:28 -0400 Date: Tue, 27 Oct 2015 10:18:20 +0800 From: Jisheng Zhang To: Ray Jui CC: , , , , , , , , , , , Subject: Re: [RFC PATCH 1/3] PCI: iproc: generate proper configuration access cycles Message-ID: <20151027101820.2d2a1368@xhacker> In-Reply-To: <562E6056.3040203@broadcom.com> References: <1445857334-6936-1-git-send-email-jszhang@marvell.com> <1445857334-6936-2-git-send-email-jszhang@marvell.com> <562E6056.3040203@broadcom.com> X-Mailer: Claws Mail 3.13.0 (GTK+ 2.24.28; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2015-10-27_02:,, signatures=0 X-Proofpoint-Spam-Details: rule=inbound_notspam policy=inbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1507310000 definitions=main-1510270042 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 26 Oct 2015 10:18:14 -0700 Ray Jui wrote: > Hi Jisheng, > > On 10/26/2015 4:02 AM, Jisheng Zhang wrote: > > Inspired by Russell King's patch[1], I found current iproc also has the > > same issue of "reading 32-bits from the command register, modifying the > > command register, and then writing it back has the effect of clearing > > any status bits that were indicating at that time" as pointed out by > > Russell. This patch fix this issue by using the pci_generic_config_write. > > > > [1]http://www.spinics.net/lists/linux-pci/msg44869.html > > > > Signed-off-by: Jisheng Zhang > > --- > > drivers/pci/host/pcie-iproc.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/pci/host/pcie-iproc.c b/drivers/pci/host/pcie-iproc.c > > index fe2efb1..0c423f2 100644 > > --- a/drivers/pci/host/pcie-iproc.c > > +++ b/drivers/pci/host/pcie-iproc.c > > @@ -111,7 +111,7 @@ static void __iomem *iproc_pcie_map_cfg_bus(struct pci_bus *bus, > > static struct pci_ops iproc_pcie_ops = { > > .map_bus = iproc_pcie_map_cfg_bus, > > .read = pci_generic_config_read32, > > - .write = pci_generic_config_write32, > > + .write = pci_generic_config_write, > > }; > > > > static void iproc_pcie_reset(struct iproc_pcie *pcie) > > > > I have already confirmed with the ASIC team that the current iProc PCIe > controller requires 32-bit aligned access into the configuration space > due to the way how it was integrated into various iProc SoCs including > NSP, Cygnus, and NS2. > > This change will prevent the driver from working properly. > > I've informed our ASIC team about this issue and all future iProc based > SoCs should be able to support 8-bit, 16-bit access and therefore > pci_generic_config_write/read can be used for those SoCs. > > Thanks, > > Ray Got it. Thanks for the information, Jisheng