From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S964813AbbJ1Uib (ORCPT ); Wed, 28 Oct 2015 16:38:31 -0400 Received: from mail-out.m-online.net ([212.18.0.10]:49043 "EHLO mail-out.m-online.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753822AbbJ1Uia (ORCPT ); Wed, 28 Oct 2015 16:38:30 -0400 X-Auth-Info: HC9ba4og6dQ8DlDsriqgnIdjK5jErgpGdIkh/7xZnKs= From: Marek Vasut To: Boris Brezillon Subject: Re: [PATCH 1/5] mtd: ofpart: grab device tree node directly from master device node Date: Wed, 28 Oct 2015 21:38:20 +0100 User-Agent: KMail/1.13.7 (Linux/3.14-2-amd64; KDE/4.13.1; x86_64; ; ) Cc: Brian Norris , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, Ezequiel Garcia , Scott Wood , Josh Wu , Robert Jarzmik , Kyungmin Park , Han Xu , Huang Shijie References: <1445913070-17950-1-git-send-email-computersforpeace@gmail.com> <201510281711.14196.marex@denx.de> <20151028173215.0c1c4e30@bbrezillon> In-Reply-To: <20151028173215.0c1c4e30@bbrezillon> MIME-Version: 1.0 Message-Id: <201510282138.20754.marex@denx.de> Content-Type: Text/Plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wednesday, October 28, 2015 at 05:32:15 PM, Boris Brezillon wrote: > Hi Marek, Hi Boris, > On Wed, 28 Oct 2015 17:11:14 +0100 > > Marek Vasut wrote: > > On Wednesday, October 28, 2015 at 08:58:13 AM, Boris Brezillon wrote: > > > Hi Brian, > > > > Hi, > > > > [...] > > > > > > Are > > > > there ever cases we want more than one (master) MTD per nand_chip? Or > > > > vice versa? > > > > > > Nope, I'd say that you always have a 1:1 relationship between a master > > > MTD device and a NAND device. > > > > Do some sorts of chipselects come into play here ? Ie. you can have one > > master with multiple NAND chips connected to it. > > Most NAND controllers support interacting with several chips (or > dies in case your chip embeds several NAND dies), but I keep thinking > each physical chip should have its own instance of nand_chip + mtd_info. > If you want to have a single mtd device aggregating several chips you > can use mtdconcat. I agree. > This leaves the multi-dies chip case, and IHMO we should represent those > chips as a single entity, and I guess that's the purpose of the > ->numchips field in nand_chip (if your chip embeds 2 dies with 2 CS > lines, then ->numchips should be 2). I'd expect this to be represented as two physical chips, no ? > Anyway, I think the whole problem here is that most NAND drivers are > mixing the concepts of NAND controller (the controller driving one or > several NAND chips) and NAND chip (a chip connected to a NAND > controller). > The NAND controller should not be represented with a nand_chip > instance, but with a nand_hw_control instance, which is rarely done > except in a few drivers. OK, understood. > I sent an RFC a while ago [1] to clarify that, but didn't have time to > post a new version. > > Best Regards, > > Boris > > [1]http://thread.gmane.org/gmane.linux.drivers.mtd/57614/focus=58552 Best regards, Marek Vasut