From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751715AbbJ2HY5 (ORCPT ); Thu, 29 Oct 2015 03:24:57 -0400 Received: from down.free-electrons.com ([37.187.137.238]:45989 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750916AbbJ2HY4 (ORCPT ); Thu, 29 Oct 2015 03:24:56 -0400 Date: Thu, 29 Oct 2015 08:24:48 +0100 From: Boris Brezillon To: Robert Jarzmik Cc: Marek Vasut , Brian Norris , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, Ezequiel Garcia , Scott Wood , Josh Wu , Kyungmin Park , Han Xu , Huang Shijie Subject: Re: [PATCH 1/5] mtd: ofpart: grab device tree node directly from master device node Message-ID: <20151029082448.2a89c791@bbrezillon> In-Reply-To: <87611qjibi.fsf@belgarion.home> References: <1445913070-17950-1-git-send-email-computersforpeace@gmail.com> <20151028171430.GC13239@google.com> <87eggek91f.fsf@belgarion.home> <201510282347.27379.marex@denx.de> <87611qjibi.fsf@belgarion.home> X-Mailer: Claws Mail 3.11.1 (GTK+ 2.24.27; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Robert, On Thu, 29 Oct 2015 07:32:33 +0100 Robert Jarzmik wrote: > Marek Vasut writes: > > >> Isn't there the case of a single NAND controller with 2 identical chips, > >> each a 8 bit NAND chip, and the controller aggregating them to offer the > >> OS a single 16-bit NAND chip ? Honestly, I don't know how this can possibly work, do you have a real example of that use case. Here are a few reasons making it impossible: 1/ NAND are accessed using specific command sequences, and those commands and addresses cycles are sent on through the data bus (AFAIR only the lower 8bits of a 16bits bus are used for those command/address cycles), so even if you connect the CLE/ALE/CS/RB pins on both chips, the one connected on the MSB side of the data bus will just receive garbage during the command/address sequences, and your program/read operations won't work 2/ NAND chips can have bad blocks, so even if you were able to address 2 chips (which according to #1 is impossible), you might try to write on a bad block on the chip connected on the MSB side of the data bus. 3/ There probably are plenty of other reasons why this is not possible ;-). Best Regards, Boris -- Boris Brezillon, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com