From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1031932AbbKEClE (ORCPT ); Wed, 4 Nov 2015 21:41:04 -0500 Received: from mx0a-0016f401.pphosted.com ([67.231.148.174]:5050 "EHLO mx0a-0016f401.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1031898AbbKECku (ORCPT ); Wed, 4 Nov 2015 21:40:50 -0500 Date: Thu, 5 Nov 2015 10:36:28 +0800 From: Jisheng Zhang To: Arnd Bergmann CC: Daniel Lezcano , , , , Subject: Re: [PATCH v2 0/3] let Marvell Berlin SoCs make use of the best delay timer Message-ID: <20151105103628.10d6f1f9@xhacker> In-Reply-To: <3751534.M13UnSz6gv@wuerfel> References: <1446560917-6318-1-git-send-email-jszhang@marvell.com> <4359736.Q4L68M2aRW@wuerfel> <5639E9DD.1080309@linaro.org> <3751534.M13UnSz6gv@wuerfel> X-Mailer: Claws Mail 3.13.0 (GTK+ 2.24.28; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2015-11-05_03:,, signatures=0 X-Proofpoint-Spam-Details: rule=inbound_notspam policy=inbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1507310000 definitions=main-1511050039 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Dear Arnd and Daniel, On Wed, 4 Nov 2015 13:19:53 +0100 Arnd Bergmann wrote: > On Wednesday 04 November 2015 12:19:57 Daniel Lezcano wrote: > > On 11/04/2015 11:30 AM, Arnd Bergmann wrote: > > > On Wednesday 04 November 2015 10:46:49 Daniel Lezcano wrote: > > >> On 11/03/2015 03:28 PM, Jisheng Zhang wrote: > > >>> In case there are several possible delay timers, we purely base the > > >>> selection on the frequency, which is suboptimal in some cases. Take > > >>> one Marvell Berlin platform for example: we have arch timer and dw-apb > > >>> timer. The arch timer freq is 25MHZ while the dw-apb timer freq is > > >>> 100MHZ, current selection would choose the dw-apb timer. But the dw > > >>> apb timer is on the APB bus while arch timer sits in CPU, the cost > > >>> of accessing the apb timer is higher than the arch timer. > > >>> > > >>> This series firstly modifies register_current_timer_delay() to choose > > >>> the highest rating delay timer: use the rating as a primary indication > > >>> and fall back to comparing the frequency if the rating is not set or > > >>> the same. Then we set the arch_delay_timer rating as 400, finally > > >>> Implement ARM delay timer for the dw_apb_timer and set its rating as 300. > > >> > > >> Hi Jisheng, Arnd, > > >> > > >> I don't feel comfortable with the rating / freq think. I am afraid this > > >> approach based on heuristic will bring a lot of complexity and > > >> workarounds in the code for a small benefit. > > >> > > >> Why don't we define a DT entry for the delay timer ? So we delegate the > > >> choice to the platform DT definition. > > > > > > That would be wrong, because the fact that Linux uses a timer to > > > optimize its udelay() function is not a feature of the hardware. > > > > True. > > > > Any ideas / suggestions for an alternative ? > > How about simply hardcoding the fact that we prefer the arch timer > over any other one for delay as I suggested earlier? > > Another idea I just had is to do nothing: According to Jisheng's > description for this series, the reason for preferring the arch > timer is that it is faster to access. However, we could argue > that this actually doesn't matter at all, because the entire > point of the ndelay()/udelay()/mdelay() functions is to waste > CPU cycles doing not much at all, so we can just as well waste > them reading the timer register than spinning on the CPU reading > the arch timer more often. > I like this "Another idea", indeed, the delay timer speed doesn't matter at all. So I just cooked v3 to simply register dw apb based delay timer. Thanks a lot for the inspiration, Jisheng