[PATCH] clk: tegra: Fix bypassing of PLLs

* [PATCH] clk: tegra: Fix bypassing of PLLs
@ 2015-11-20 15:11 Jon Hunter
  2015-11-20 16:43 ` Rhyland Klein
                   ` (2 more replies)
  0 siblings, 3 replies; 12+ messages in thread
From: Jon Hunter @ 2015-11-20 15:11 UTC (permalink / raw)
  To: Peter De Schrijver, Prashant Gaikwad, Michael Turquette,
	Stephen Boyd, Stephen Warren, Thierry Reding, Alexandre Courbot
  Cc: linux-clk, linux-tegra, linux-kernel, Rhyland Klein, Jon Hunter

The _clk_disable_pll() function will attempt to place a PLL into bypass
if the TEGRA_PLL_BYPASS is specified for the PLL and then disable the PLL
by clearing the enable bit. To place the PLL into bypass, the bypass bit
needs to be set and not cleared. Fix this by setting the bypass bit and
not clearing it.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
---
 drivers/clk/tegra/clk-pll.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index d6d4ecb88e94..e5aa9c87df4c 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -312,7 +312,7 @@ static void _clk_pll_disable(struct clk_hw *hw)
 
 	val = pll_readl_base(pll);
 	if (pll->params->flags & TEGRA_PLL_BYPASS)
-		val &= ~PLL_BASE_BYPASS;
+		val |= PLL_BASE_BYPASS;
 	val &= ~PLL_BASE_ENABLE;
 	pll_writel_base(val, pll);
 
-- 
2.1.4


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