From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1163222AbbKTRPc (ORCPT ); Fri, 20 Nov 2015 12:15:32 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:57054 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1759660AbbKTRP3 (ORCPT ); Fri, 20 Nov 2015 12:15:29 -0500 Date: Fri, 20 Nov 2015 09:15:27 -0800 From: Stephen Boyd To: Jon Hunter Cc: Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Warren , Thierry Reding , Alexandre Courbot , linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Rhyland Klein Subject: Re: [PATCH] clk: tegra: Fix bypassing of PLLs Message-ID: <20151120171527.GL32672@codeaurora.org> References: <1448032264-29622-1-git-send-email-jonathanh@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1448032264-29622-1-git-send-email-jonathanh@nvidia.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 11/20, Jon Hunter wrote: > The _clk_disable_pll() function will attempt to place a PLL into bypass > if the TEGRA_PLL_BYPASS is specified for the PLL and then disable the PLL > by clearing the enable bit. To place the PLL into bypass, the bypass bit > needs to be set and not cleared. Fix this by setting the bypass bit and > not clearing it. > > Signed-off-by: Jon Hunter > --- Fixes tag? It looks like this has been wrong from the beginning of time. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project