From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754102AbbKWI5Z (ORCPT ); Mon, 23 Nov 2015 03:57:25 -0500 Received: from down.free-electrons.com ([37.187.137.238]:48004 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754071AbbKWI5W (ORCPT ); Mon, 23 Nov 2015 03:57:22 -0500 Date: Mon, 23 Nov 2015 09:57:19 +0100 From: Maxime Ripard To: Jens Kuske Cc: Chen-Yu Tsai , Michael Turquette , Linus Walleij , Rob Herring , Philipp Zabel , Emilio =?iso-8859-1?Q?L=F3pez?= , Vishnu Patekar , Hans de Goede , devicetree , linux-arm-kernel , linux-kernel , linux-sunxi Subject: Re: [PATCH v4 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI Message-ID: <20151123085719.GT32142@lukather> References: <1445964626-6484-1-git-send-email-jenskuske@gmail.com> <1445964626-6484-6-git-send-email-jenskuske@gmail.com> <563614A3.6060805@gmail.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="yQifGgTvVVJcdOYJ" Content-Disposition: inline In-Reply-To: <563614A3.6060805@gmail.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --yQifGgTvVVJcdOYJ Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi, On Sun, Nov 01, 2015 at 02:33:23PM +0100, Jens Kuske wrote: > >> + bus_gates: clk@01c20060 { > >> + #clock-cells =3D <1>; > >> + compatible =3D "allwinner,sun8i-h3-bus-gates-c= lk"; > >> + reg =3D <0x01c20060 0x14>; > >> + clocks =3D <&ahb1>, <&ahb2>, <&apb1>, <&apb2>; > >> + clock-names =3D "ahb1", "ahb2", "apb1", "apb2"; > >> + clock-indices =3D <5>, <6>, <8>, > >> + <9>, <10>, <13>, > >> + <14>, <17>, <18>, > >> + <19>, <20>, > >> + <21>, <23>, > >> + <24>, <25>, > >> + <26>, <27>, > >> + <28>, <29>, > >> + <30>, <31>, <32>, > >> + <35>, <36>, <37>, > >> + <40>, <41>, <43>, > >> + <44>, <52>, <53>, > >> + <54>, <64>, > >> + <65>, <69>, <72>, > >> + <76>, <77>, <78>, > >> + <96>, <97>, <98>, > >> + <112>, <113>, > >> + <114>, <115>, <116>, > >> + <128>, <135>; > >> + clock-output-names =3D "ahb1_ce", "ahb1_dma", = "ahb1_mmc0", > >> + "ahb1_mmc1", "ahb1_mmc2", "ahb= 1_nand", > >> + "ahb1_sdram", "ahb2_gmac", "ah= b1_ts", > >> + "ahb1_hstimer", "ahb1_spi0", > >> + "ahb1_spi1", "ahb1_otg", > >> + "ahb1_otg_ehci0", "ahb1_ehic1", > >=20 > > ahb1_ehci1? Same for the following 3 lines. > I'll fix them... > >=20 > >> + "ahb1_ehic2", "ahb1_ehic3", > >> + "ahb1_otg_ohci0", "ahb2_ohic1", > >> + "ahb2_ohic2", "ahb2_ohic3", "a= hb1_ve", > >> + "ahb1_lcd0", "ahb1_lcd1", "ahb= 1_deint", > >> + "ahb1_csi", "ahb1_tve", "ahb1_= hdmi", > >> + "ahb1_de", "ahb1_gpu", "ahb1_m= sgbox", > >> + "ahb1_spinlock", "apb1_codec", > >> + "apb1_spdif", "apb1_pio", "apb= 1_ths", > >> + "apb1_i2s0", "apb1_i2s1", "apb= 1_i2s2", > >> + "apb2_i2c0", "apb2_i2c1", "apb= 2_i2c2", > >> + "apb2_uart0", "apb2_uart1", > >> + "apb2_uart2", "apb2_uart3", "a= pb2_scr", > >> + "ahb1_ephy", "ahb1_dbg"; > >=20 > > If it weren't for the last 2 clocks, we could cleanly split out apb1 an= d apb2 > > gates. Having a separate AHB clock gate taking 2 addresses seems messy > > as well. :( >=20 > Well, maybe we still should do that, if we split the resets too at least > apb[12] would line up again. >=20 > I don't know what to do with these bus things any more, all variants I > sent had issues somewhere... AFAIK, Arnd had some objections, but he never got back to us when we explained how the hardware was laid out, so I don't know if they still apply. > >> + }; > >> + > >> + mmc0_clk: clk@01c20088 { > >> + #clock-cells =3D <1>; > >> + compatible =3D "allwinner,sun4i-a10-mmc-clk"; > >> + reg =3D <0x01c20088 0x4>; > >> + clocks =3D <&osc24M>, <&pll6 0>, <&pll8 0>; > >> + clock-output-names =3D "mmc0", > >> + "mmc0_output", > >> + "mmc0_sample"; > >> + }; > >> + > >> + mmc1_clk: clk@01c2008c { > >> + #clock-cells =3D <1>; > >> + compatible =3D "allwinner,sun4i-a10-mmc-clk"; > >> + reg =3D <0x01c2008c 0x4>; > >> + clocks =3D <&osc24M>, <&pll6 0>, <&pll8 0>; > >> + clock-output-names =3D "mmc1", > >> + "mmc1_output", > >> + "mmc1_sample"; > >> + }; > >> + > >> + mmc2_clk: clk@01c20090 { > >> + #clock-cells =3D <1>; > >> + compatible =3D "allwinner,sun4i-a10-mmc-clk"; > >> + reg =3D <0x01c20090 0x4>; > >> + clocks =3D <&osc24M>, <&pll6 0>, <&pll8 0>; > >> + clock-output-names =3D "mmc2", > >> + "mmc2_output", > >> + "mmc2_sample"; > >> + }; > >> + > >> + mbus_clk: clk@01c2015c { > >> + #clock-cells =3D <0>; > >> + compatible =3D "allwinner,sun8i-a23-mbus-clk"; > >> + reg =3D <0x01c2015c 0x4>; > >> + clocks =3D <&osc24M>, <&pll6 1>, <&pll5>; > >> + clock-output-names =3D "mbus"; > >> + }; > >> + }; > >> + > >> + soc { > >> + compatible =3D "simple-bus"; > >> + #address-cells =3D <1>; > >> + #size-cells =3D <1>; > >> + ranges; > >> + > >> + dma: dma-controller@01c02000 { > >> + compatible =3D "allwinner,sun8i-h3-dma"; > >> + reg =3D <0x01c02000 0x1000>; > >> + interrupts =3D ; > >> + clocks =3D <&bus_gates 6>; > >> + resets =3D <&bus_rst 6>; > >> + #dma-cells =3D <1>; > >> + }; > >> + > >> + mmc0: mmc@01c0f000 { > >> + compatible =3D "allwinner,sun5i-a13-mmc"; > >> + reg =3D <0x01c0f000 0x1000>; > >> + clocks =3D <&bus_gates 8>, > >> + <&mmc0_clk 0>, > >> + <&mmc0_clk 1>, > >> + <&mmc0_clk 2>; > >> + clock-names =3D "ahb", > >> + "mmc", > >> + "output", > >> + "sample"; > >> + resets =3D <&bus_rst 8>; > >> + reset-names =3D "ahb"; > >> + interrupts =3D ; > >> + status =3D "disabled"; > >> + #address-cells =3D <1>; > >> + #size-cells =3D <0>; > >> + }; > >> + > >> + mmc1: mmc@01c10000 { > >> + compatible =3D "allwinner,sun5i-a13-mmc"; > >> + reg =3D <0x01c10000 0x1000>; > >> + clocks =3D <&bus_gates 9>, > >> + <&mmc1_clk 0>, > >> + <&mmc1_clk 1>, > >> + <&mmc1_clk 2>; > >> + clock-names =3D "ahb", > >> + "mmc", > >> + "output", > >> + "sample"; > >> + resets =3D <&bus_rst 9>; > >> + reset-names =3D "ahb"; > >> + interrupts =3D ; > >> + status =3D "disabled"; > >> + #address-cells =3D <1>; > >> + #size-cells =3D <0>; > >> + }; > >> + > >> + mmc2: mmc@01c11000 { > >> + compatible =3D "allwinner,sun5i-a13-mmc"; > >> + reg =3D <0x01c11000 0x1000>; > >> + clocks =3D <&bus_gates 10>, > >> + <&mmc2_clk 0>, > >> + <&mmc2_clk 1>, > >> + <&mmc2_clk 2>; > >> + clock-names =3D "ahb", > >> + "mmc", > >> + "output", > >> + "sample"; > >> + resets =3D <&bus_rst 10>; > >> + reset-names =3D "ahb"; > >> + interrupts =3D ; > >> + status =3D "disabled"; > >> + #address-cells =3D <1>; > >> + #size-cells =3D <0>; > >> + }; > >> + > >> + pio: pinctrl@01c20800 { > >> + compatible =3D "allwinner,sun8i-h3-pinctrl"; > >> + reg =3D <0x01c20800 0x400>; > >> + interrupts =3D , > >> + ; > >> + clocks =3D <&bus_gates 69>; > >> + gpio-controller; > >> + #gpio-cells =3D <3>; > >> + interrupt-controller; > >> + #interrupt-cells =3D <2>; > >> + > >> + uart0_pins_a: uart0@0 { > >> + allwinner,pins =3D "PA4", "PA5"; > >> + allwinner,function =3D "uart0"; > >> + allwinner,drive =3D ; > >> + allwinner,pull =3D ; > >> + }; > >> + > >> + mmc0_pins_a: mmc0@0 { > >> + allwinner,pins =3D "PF0", "PF1", "PF2"= , "PF3", > >> + "PF4", "PF5"; > >> + allwinner,function =3D "mmc0"; > >> + allwinner,drive =3D ; > >> + allwinner,pull =3D ; > >> + }; > >> + > >> + mmc0_cd_pin: mmc0_cd_pin@0 { > >> + allwinner,pins =3D "PF6"; > >> + allwinner,function =3D "gpio_in"; > >> + allwinner,drive =3D ; > >> + allwinner,pull =3D ; > >> + }; > >=20 > > This should be in the board DTS, unless this is the reference design, > > in which case you should name the label like "mmc0_cd_pin_reference_des= ign". > >=20 >=20 > The datasheet mentions SDC0_DET function on PF6, so I thought this is > sort of fixed to this pin now. All designs I've seen use this pin. Why is it set as a gpio then if it is a separate function? Thanks! Maxime --=20 Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com --yQifGgTvVVJcdOYJ Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBAgAGBQJWUtTvAAoJEBx+YmzsjxAgPYUP/iUtY5l3h+2mMeU6dgfCEXDz YKmVM03YZsoMg2h+oE18R4CwLmIz2qXXHYdVE4IGFeWvgT5Y0zA8ZkCChwyiIrUu /FJkvaPnV91++YJhhIh9X4y5Uiu/7W/VZW0Omls150T2IgxwP8JmHRbSB2fNR2dm cV37pKBNJn/sY5gkhqyXn0GNslxu2d5830gs5MUmCd7bCXNCdYXQGM3xMqjX6krw HCKstMAEz7z7+t6dnj5oncPhavlMtU0E4REQIY2ux8zc2LwrEe8oKc2F98k0NoFr +5ZJuBw07p3jyvQtMD1hHOvxDmU1u20iKhVqDsy4KXE780Ubeud5SAXWkP0RPQd9 MIap2hyNBRUBgGDxrHSp8m2TRfeqOQPH8qaqy2z3+Qpo4ELucgEjxpRzSpYtNxNj iA6d3ZKn4DJt/fAWPfJaiY/LBaGf/s8xTJ6ejfE70UfpqVeeiL6BPY1ZOOKPmNqT 1ezNorqyk1eigUzNpri4I6HKIgiYZh5gpGB+F+wNqlqAq+zwgSasMBne7C9BFJMD WA+omWCkmkHleVK4lwZuLtpwgO5kdzoqtFVKRgzXXNQ/paR9jZMgkhlz+lY1U2+l A9sKN2ms0WOQRx+838OersbH1qWszuRhQRfEz0k+f0299926AQKX++jmOhp3VVlA 3uS9s3tIG8MdpbDvo10F =wwun -----END PGP SIGNATURE----- --yQifGgTvVVJcdOYJ--