From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756845AbbLBINX (ORCPT ); Wed, 2 Dec 2015 03:13:23 -0500 Received: from mail.kernel.org ([198.145.29.136]:48549 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755287AbbLBINV (ORCPT ); Wed, 2 Dec 2015 03:13:21 -0500 Date: Wed, 2 Dec 2015 16:13:06 +0800 From: Shawn Guo To: Stefan Agner Cc: kernel@pengutronix.de, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, linux@arm.linux.org.uk, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] ARM: dts: vf610: use reset values for L2 cache latencies Message-ID: <20151202081306.GR692@tiger> References: <1448935166-2697-1-git-send-email-stefan@agner.ch> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1448935166-2697-1-git-send-email-stefan@agner.ch> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Nov 30, 2015 at 05:59:26PM -0800, Stefan Agner wrote: > Linux on Vybrid used several different L2 latencies so far, none > of them seem to be the right ones. According to the application note > AN4947 ("Understanding Vybrid Architecture"), the tag portion runs > on CPU clock and is inside the L2 cache controller, whereas the data > portion is stored in the external SRAM running on platform clock. > Hence it is likely that the correct value requires a higher data > latency then tag latency. > > These are the values which have been used so far: > - The mainline values: > arm,data-latency = <1 1 1>; > arm,tag-latency = <2 2 2>; > Those values have lead to problems on higher clocks. They look > like a poor translation from the reset values (missing +1 offset > and a mix up between tag/latency values). > - The Linux 3.0 (SoC vendor BSP) values (converted to DT notation): > arm,data-latency = <4 2 3> > arm,tag-latency = <4 2 3> > The cache initialization function along with the value matches the > i.MX6 code from the same kernel, so it seems that those values have > just been copied. > - The Colibri values: > arm,data-latency = <2 1 2>; > arm,tag-latency = <3 2 3>; > Those were a mix between the values of the Linux 3.0 based BSP and > the mainline values above. > - The SoC Reset values (converted to DT notation): > arm,data-latency = <3 3 3>; > arm,tag-latency = <2 2 2>; > > So far there is no official statement on what the correct values are. > See also the related Freescale community thread: > https://community.freescale.com/message/579785#579785 > > For now, the reset values seem to be the best bet. Remove all other > "bogus" values and use the reset value on vf610.dtsi level. > > Signed-off-by: Stefan Agner > --- > Hi Shawn, > > Any chance to get this into 4.4? I can try. Generally, upstream maintainers are becoming more strict for -rc inclusion after -rc3 phase. Do you have any user stories about why this is a critical/urgent fix? If we send this a critical fix for 4.4-rc inclusion, do we need to Cc stable? Shawn > > -- > Stefan > > arch/arm/boot/dts/vf610-colibri.dtsi | 5 ----- > arch/arm/boot/dts/vf610.dtsi | 2 +- > 2 files changed, 1 insertion(+), 6 deletions(-) > > diff --git a/arch/arm/boot/dts/vf610-colibri.dtsi b/arch/arm/boot/dts/vf610-colibri.dtsi > index 19fe045..2d7eab7 100644 > --- a/arch/arm/boot/dts/vf610-colibri.dtsi > +++ b/arch/arm/boot/dts/vf610-colibri.dtsi > @@ -18,8 +18,3 @@ > reg = <0x80000000 0x10000000>; > }; > }; > - > -&L2 { > - arm,data-latency = <2 1 2>; > - arm,tag-latency = <3 2 3>; > -}; > diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi > index 5f8eb1b..58bc6e4 100644 > --- a/arch/arm/boot/dts/vf610.dtsi > +++ b/arch/arm/boot/dts/vf610.dtsi > @@ -19,7 +19,7 @@ > reg = <0x40006000 0x1000>; > cache-unified; > cache-level = <2>; > - arm,data-latency = <1 1 1>; > + arm,data-latency = <3 3 3>; > arm,tag-latency = <2 2 2>; > }; > }; > -- > 2.6.2 > >