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From: Mark Rutland <mark.rutland@arm.com>
To: "Suzuki K. Poulose" <Suzuki.Poulose@arm.com>
Cc: linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, arm@kernel.org,
	punit.agrawal@arm.com, peterz@infradead.org
Subject: Re: [PATCH v5 05/11] arm-cci PMU: Delay counter writes to pmu_enable
Date: Mon, 11 Jan 2016 11:24:43 +0000	[thread overview]
Message-ID: <20160111112443.GI6499@leverpostej> (raw)
In-Reply-To: <56938D2B.7050700@arm.com>

On Mon, Jan 11, 2016 at 11:08:27AM +0000, Suzuki K. Poulose wrote:
> On 11/01/16 10:46, Mark Rutland wrote:
> >On Tue, Jan 05, 2016 at 09:59:13AM +0000, Suzuki K. Poulose wrote:
> >>On 04/01/16 19:24, Mark Rutland wrote:
> >>>On Mon, Jan 04, 2016 at 11:54:44AM +0000, Suzuki K. Poulose wrote:
> >>The pmu is not disabled while we are in overflow irq handler. Hence there may
> >>not be a pmu_enable() which would set the period for the counter which
> >>overflowed, if defer the write in that case. Is that assumption wrong ?
> >
> >As the driver stands today, yes.
> >
> >However, wouldn't it make more sense to disable the PMU for the overflow
> >handler, such that we can reuse the batching logic?
> 
> None of the PMU drivers do that AFAIK.

I see.

The Intel PMU driver disables the PMU for the interrupt handler; see
intel_pmu_handle_irq in arch/x86/kernel/cpu/perf_event_intel.c. It looks
like that's a special-case for sampling.

I guess we may have the only case where it makes sense to batch counter
writes as opposed to batching configuration writes.

> Hence, didn't want to change it for CCI. We could use the batching
> logic, if decide to do so. I can go ahead with that if there are no
> other side effects with that.

We'll lose events regardless as our RMW sequence will race against the
counters. Batching will make that window slightly larger, but other than
that I don't see a problem.

Thanks,
Mark.

  reply	other threads:[~2016-01-11 11:25 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-01-04 11:54 [PATCH v5 00/11] arm-cci: PMU updates Suzuki K. Poulose
2016-01-04 11:54 ` [PATCH v5 01/11] arm-cci: Define CCI counter period Suzuki K. Poulose
2016-01-04 18:27   ` Mark Rutland
2016-01-05  9:50     ` Suzuki K. Poulose
2016-01-04 11:54 ` [PATCH v5 02/11] arm-cci: Refactor pmu_write_counter Suzuki K. Poulose
2016-01-04 19:01   ` Mark Rutland
2016-01-04 11:54 ` [PATCH v5 03/11] arm-cci: Group writes to counter Suzuki K. Poulose
2016-01-04 19:03   ` Mark Rutland
2016-01-05 10:51     ` Suzuki K. Poulose
2016-01-11 10:44       ` Mark Rutland
2016-01-11 10:48         ` Suzuki K. Poulose
2016-01-04 11:54 ` [PATCH v5 04/11] arm-cci: Refactor CCI PMU enable/disable methods Suzuki K. Poulose
2016-01-04 11:54 ` [PATCH v5 05/11] arm-cci PMU: Delay counter writes to pmu_enable Suzuki K. Poulose
2016-01-04 19:24   ` Mark Rutland
2016-01-05  9:59     ` Suzuki K. Poulose
2016-01-11 10:46       ` Mark Rutland
2016-01-11 11:08         ` Suzuki K. Poulose
2016-01-11 11:24           ` Mark Rutland [this message]
2016-01-11 18:12             ` Suzuki K. Poulose
2016-01-04 11:54 ` [PATCH v5 06/11] arm-cci: Get the status of a counter Suzuki K. Poulose
2016-01-04 11:54 ` [PATCH v5 07/11] arm-cci: Add routines to save/restore all counters Suzuki K. Poulose
2016-01-11 10:50   ` Mark Rutland
2016-01-11 10:58     ` Suzuki K. Poulose
2016-01-04 11:54 ` [PATCH v5 08/11] arm-cci: Provide hook for writing to PMU counters Suzuki K. Poulose
2016-01-11 10:54   ` Mark Rutland
2016-01-11 12:14     ` Suzuki K. Poulose
2016-01-04 11:54 ` [PATCH v5 09/11] arm-cci: CCI-500: Work around PMU counter writes Suzuki K. Poulose
2016-01-04 11:54 ` [PATCH v5 10/11] arm-cci500: Rearrange PMU driver for code sharing with CCI-550 PMU Suzuki K. Poulose
2016-01-04 11:54 ` [PATCH v5 11/11] arm-cci: CoreLink CCI-550 PMU driver Suzuki K. Poulose

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