[PATCH RFC 00/15] mmc: sunxi: Support vqmmc regulator and eMMC DDR modes

[PATCH RFC 00/15] mmc: sunxi: Support vqmmc regulator and eMMC DDR modes

[Chen-Yu Tsai]

Hi everyone,

This series adds support for vqmmc regulator and eMMC DDR modes for
sunxi-mmc. Allwinner's MMC controller supports eMMC 4.41 on earlier
SoCs, and up to 5.0 on latest ones. UHS-1 modes are also supported
by the hardware, but these are not covered in this series, as no
boards have dedicated regulators for vqmmc.

To support these faster modes, these patches adds vqmmc regulator
support, which is used by the mmc core to switch to faster modes,
even if the signaling voltage is fixed. Signal voltage switching
support is also added, but not tested, as no available hardware has
a dedicated vqmmc regulator.

Support for eMMC reset in the controller, vs a GPIO and pwrseq, is
also added where applicable.

Patch 1 documents the mmc host init sequence. When the driver was
ported, this part was copied verbatim and not documented. With inline
comments from later SDKs and datasheet register definitions, this part
is now clearer.

Patch 2 makes the .set_ios callback return on errors from
mmc_regulator_set_ocr.

Patch 3 adds support (enabling/disable, and voltage control) for vqmmc
regulator to sunxi-mmc.

Patch 4 adds support signal voltage switch for the mmc controller. The
Allwinner MMC controller uses a special bit for sending signal voltage
switching command.

Patch 5 adds timing delays for MMC_DDR52 mode.

Patch 6 adds support for 8 bit eMMC DDR52 mode. Under this mode, the
controller must run at twice the card clock, and different timing delays
are needed.

Patch 7 enables eMMC HS-DDR for sunxi-mmc.

Patch 8 adds mmc3 pins for 8 bit emmc for A31/A31s.

Patch 9 switches from mmc2 to mmc3 for the onboard eMMC on Sinlinx
SinA31s. According to Allwinner, only mmc3 supports eMMC DDR52 on
A31/A31s.

Patch 10 adds the eMMC reset pin to the emmc pingroup for A23/A33.

Patch 11 enables eMMC hardware reset and eMMC DDR52 mode for SinA33.

Patch 12 switches A80 to sun9i specific mmc compatible. A80 has different
timing delays, and a larger FIFO (TODO).

Patch 13 adds the eMMC reset pin to the emmc pingroup for A80.

Patch 14 enables eMMC hardware reset and eMMC DDR52 mode for A80 Optimus.

Patch 15 enables eMMC hardware reset and eMMC DDR52 mode for Cubieboard4.

Chen-Yu Tsai (15):
  mmc: sunxi: Document host init sequence
  mmc: sunxi: Return error on mmc_regulator_set_ocr() fail in .set_ios
    op
  mmc: sunxi: Block signal voltage switching (CMD11)
  mmc: sunxi: Support vqmmc regulator
  mmc: sunxi: Support MMC_DDR52 timing modes
  mmc: sunxi: Support 8 bit eMMC DDR transfer modes
  mmc: sunxi: Enable eMMC HS-DDR (MMC_CAP_1_8V_DDR) support
  ARM: dts: sun6i: Add mmc3 pins for 8 bit emmc
  ARM: dts: sun6i: sina31s: Switch to mmc3 for onboard eMMC
  ARM: dts: sun8i: Include SDC2_RST pin in mmc2_8bit_pins
  ARM: dts: sun8i: sina33: Enable hardware reset and HS-DDR for eMMC
  ARM: dts: sun9i: Use sun9i specific mmc compatible
  ARM: dts: sun9i: Include SDC2_RST pin in mmc2_8bit_pins
  ARM: dts: sun9i: a80-optimus: Enable hardware reset and HS-DDR for
    eMMC
  ARM: dts: sun9i: cubieboard4: Enable hardware reset and HS-DDR for
    eMMC

 arch/arm/boot/dts/sun6i-a31.dtsi               | 10 +++
 arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi |  6 +-
 arch/arm/boot/dts/sun8i-a23-a33.dtsi           |  2 +-
 arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts |  3 +
 arch/arm/boot/dts/sun9i-a80-cubieboard4.dts    |  6 ++
 arch/arm/boot/dts/sun9i-a80-optimus.dts        |  6 ++
 arch/arm/boot/dts/sun9i-a80.dtsi               | 11 +--
 drivers/mmc/host/sunxi-mmc.c                   | 98 +++++++++++++++++++++++---
 8 files changed, 126 insertions(+), 16 deletions(-)

-- 
2.7.0.rc3

[PATCH RFC 01/15] mmc: sunxi: Document host init sequence

[Chen-Yu Tsai]

sunxi_mmc_init_host() originated from Allwinner kernel sources. The
magic numbers written to various registers was never documented.

Add comments for values found in Allwinner user manuals.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 drivers/mmc/host/sunxi-mmc.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
index 83de82bceafc..cce5ca540857 100644
--- a/drivers/mmc/host/sunxi-mmc.c
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -284,16 +284,28 @@ static int sunxi_mmc_init_host(struct mmc_host *mmc)
 	if (sunxi_mmc_reset_host(host))
 		return -EIO;
 
+	/*
+	 * Burst 8 transfers, RX trigger level: 7, TX trigger level: 8
+	 *
+	 * TODO: sun9i has a larger FIFO and supports higher trigger values
+	 */
 	mmc_writel(host, REG_FTRGL, 0x20070008);
+	/* Maximum timeout value */
 	mmc_writel(host, REG_TMOUT, 0xffffffff);
+	/* Unmask SDIO interrupt if needed */
 	mmc_writel(host, REG_IMASK, host->sdio_imask);
+	/* Clear all pending interrupts */
 	mmc_writel(host, REG_RINTR, 0xffffffff);
+	/* Debug register? undocumented */
 	mmc_writel(host, REG_DBGC, 0xdeb);
+	/* Enable CEATA support */
 	mmc_writel(host, REG_FUNS, SDXC_CEATA_ON);
+	/* Set DMA descriptor list base address */
 	mmc_writel(host, REG_DLBA, host->sg_dma);
 
 	rval = mmc_readl(host, REG_GCTRL);
 	rval |= SDXC_INTERRUPT_ENABLE_BIT;
+	/* Undocumented, but found in Allwinner code */
 	rval &= ~SDXC_ACCESS_DONE_DIRECT;
 	mmc_writel(host, REG_GCTRL, rval);
 
-- 
2.7.0.rc3

[PATCH RFC 02/15] mmc: sunxi: Return error on mmc_regulator_set_ocr() fail in .set_ios op

[Chen-Yu Tsai]

Let .set_ios() fail if mmc_regulator_set_ocr() fails to enable and set a
proper voltage for vmmc.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 drivers/mmc/host/sunxi-mmc.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
index cce5ca540857..790f01662b4e 100644
--- a/drivers/mmc/host/sunxi-mmc.c
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -711,7 +711,10 @@ static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 		break;
 
 	case MMC_POWER_UP:
-		mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
+		host->ferror = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
+						     ios->vdd);
+		if (host->ferror)
+			return;
 
 		host->ferror = sunxi_mmc_init_host(mmc);
 		if (host->ferror)
-- 
2.7.0.rc3

[PATCH RFC 03/15] mmc: sunxi: Block signal voltage switching (CMD11)

[Chen-Yu Tsai]

Allwinner's mmc controller supports signal voltage switching. This is
supported in code in Allwinner's kernel. However, publicly available
boards all tie it to a fixed 3.0/3.3V regulator, with options to tie
it to 1.8V for eMMC on some.

Since Allwinner's kernel is an ancient 3.4, it is hard to say whether
adapting it's code to a modern mainline kernel would work. Block signal
voltage switching until someone has proper hardware to implement and
test this.

This only affects SD UHS-1 modes, as eMMC switches the voltage directly
without any signaling.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 drivers/mmc/host/sunxi-mmc.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
index 790f01662b4e..0495ae7da6d6 100644
--- a/drivers/mmc/host/sunxi-mmc.c
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -816,6 +816,20 @@ static void sunxi_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
 		}
 	}
 
+	/*
+	 * TODO Support signal voltage switching
+	 *
+	 * Compared to Allwinner's kernel, recent updates in the mmc core
+	 * mean this should be as easy as setting the flags in cmd_val and
+	 * imask, and waiting for it to finish. However no boards support
+	 * this so this cannot be tested. Block it for now.
+	 */
+	if (cmd->opcode == SD_SWITCH_VOLTAGE) {
+		mrq->cmd->error = -EPERM;
+		mmc_request_done(mmc, mrq);
+		return;
+	}
+
 	if (cmd->opcode == MMC_GO_IDLE_STATE) {
 		cmd_val |= SDXC_SEND_INIT_SEQUENCE;
 		imask |= SDXC_COMMAND_DONE;
-- 
2.7.0.rc3

[PATCH RFC 04/15] mmc: sunxi: Support vqmmc regulator

[Chen-Yu Tsai]

eMMC chips require 2 power supplies, vmmc for internal logic, and vqmmc
for driving output buffers. vqmmc also controls signaling voltage. Most
boards we've seen use the same regulator for both, nevertheless the 2
have different usages, and should be set separately.

This patch adds support for vqmmc regulator supply, including voltage
switching. The MMC core can use this to try different signaling voltages
for eMMC.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 drivers/mmc/host/sunxi-mmc.c | 31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
index 0495ae7da6d6..4bec87458317 100644
--- a/drivers/mmc/host/sunxi-mmc.c
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -28,6 +28,7 @@
 #include <linux/dma-mapping.h>
 #include <linux/slab.h>
 #include <linux/reset.h>
+#include <linux/regulator/consumer.h>
 
 #include <linux/of_address.h>
 #include <linux/of_gpio.h>
@@ -256,6 +257,9 @@ struct sunxi_mmc_host {
 	struct mmc_request *mrq;
 	struct mmc_request *manual_stop_mrq;
 	int		ferror;
+
+	/* vqmmc */
+	bool		vqmmc_enabled;
 };
 
 static int sunxi_mmc_reset_host(struct sunxi_mmc_host *host)
@@ -716,6 +720,16 @@ static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 		if (host->ferror)
 			return;
 
+		if (!IS_ERR(mmc->supply.vqmmc)) {
+			host->ferror = regulator_enable(mmc->supply.vqmmc);
+			if (host->ferror) {
+				dev_err(mmc_dev(mmc),
+					"failed to enable vqmmc\n");
+				return;
+			}
+			host->vqmmc_enabled = true;
+		}
+
 		host->ferror = sunxi_mmc_init_host(mmc);
 		if (host->ferror)
 			return;
@@ -727,6 +741,9 @@ static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 		dev_dbg(mmc_dev(mmc), "power off!\n");
 		sunxi_mmc_reset_host(host);
 		mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
+		if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled)
+			regulator_disable(mmc->supply.vqmmc);
+		host->vqmmc_enabled = false;
 		break;
 	}
 
@@ -758,6 +775,19 @@ static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 	}
 }
 
+static int sunxi_mmc_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)
+{
+	/* vqmmc regulator is available */
+	if (!IS_ERR(mmc->supply.vqmmc))
+		return mmc_regulator_set_vqmmc(mmc, ios);
+
+	/* no vqmmc regulator, assume fixed regulator at 3/3.3V */
+	if (mmc->ios.signal_voltage == MMC_SIGNAL_VOLTAGE_330)
+		return 0;
+
+	return -EINVAL;
+}
+
 static void sunxi_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
 {
 	struct sunxi_mmc_host *host = mmc_priv(mmc);
@@ -923,6 +953,7 @@ static struct mmc_host_ops sunxi_mmc_ops = {
 	.get_ro		 = mmc_gpio_get_ro,
 	.get_cd		 = mmc_gpio_get_cd,
 	.enable_sdio_irq = sunxi_mmc_enable_sdio_irq,
+	.start_signal_voltage_switch = sunxi_mmc_volt_switch,
 	.hw_reset	 = sunxi_mmc_hw_reset,
 	.card_busy	 = sunxi_mmc_card_busy,
 };
-- 
2.7.0.rc3

[PATCH RFC 05/15] mmc: sunxi: Support MMC_DDR52 timing modes

[Chen-Yu Tsai]

DDR transfer modes include UHS-1 DDR50 and MMC HS-DDR (or MMC_DDR52).
Consider MMC_DDR52 when setting clock delays.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 drivers/mmc/host/sunxi-mmc.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
index 4bec87458317..b403a2433eec 100644
--- a/drivers/mmc/host/sunxi-mmc.c
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -687,7 +687,8 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
 		oclk_dly = host->clk_delays[SDXC_CLK_25M].output;
 		sclk_dly = host->clk_delays[SDXC_CLK_25M].sample;
 	} else if (rate <= 50000000) {
-		if (ios->timing == MMC_TIMING_UHS_DDR50) {
+		if (ios->timing == MMC_TIMING_UHS_DDR50 ||
+		    ios->timing == MMC_TIMING_MMC_DDR52) {
 			oclk_dly = host->clk_delays[SDXC_CLK_50M_DDR].output;
 			sclk_dly = host->clk_delays[SDXC_CLK_50M_DDR].sample;
 		} else {
@@ -762,7 +763,8 @@ static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 
 	/* set ddr mode */
 	rval = mmc_readl(host, REG_GCTRL);
-	if (ios->timing == MMC_TIMING_UHS_DDR50)
+	if (ios->timing == MMC_TIMING_UHS_DDR50 ||
+	    ios->timing == MMC_TIMING_MMC_DDR52)
 		rval |= SDXC_DDR_MODE;
 	else
 		rval &= ~SDXC_DDR_MODE;
-- 
2.7.0.rc3

[PATCH RFC 06/15] mmc: sunxi: Support 8 bit eMMC DDR transfer modes

[Chen-Yu Tsai]

Allwinner's MMC controller needs to run at double the card clock rate
for 8 bit DDR transfer modes. Interestingly, this is not needed for
4 bit DDR transfers.

Different clock delays are needed for 8 bit eMMC DDR, due to the
increased module clock rate. For the A80 though, the same values for
4 bit and 8 bit are shared. The new values for the other SoCs were from
A83T user manual's "new timing mode" default values, which describes
them in clock phase, rather than delay periods. These values were used
without any modification. They may not be correct, but they work.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 drivers/mmc/host/sunxi-mmc.c | 33 ++++++++++++++++++++++++++-------
 1 file changed, 26 insertions(+), 7 deletions(-)

diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
index b403a2433eec..d05928091b34 100644
--- a/drivers/mmc/host/sunxi-mmc.c
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -215,6 +215,7 @@
 #define SDXC_CLK_25M		1
 #define SDXC_CLK_50M		2
 #define SDXC_CLK_50M_DDR	3
+#define SDXC_CLK_50M_DDR_8BIT	4
 
 struct sunxi_mmc_clk_delay {
 	u32 output;
@@ -656,11 +657,17 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
 				  struct mmc_ios *ios)
 {
 	u32 rate, oclk_dly, rval, sclk_dly;
+	u32 clock = ios->clock;
 	int ret;
 
-	rate = clk_round_rate(host->clk_mmc, ios->clock);
+	/* 8 bit DDR requires a higher module clock */
+	if (ios->timing == MMC_TIMING_MMC_DDR52 &&
+	    ios->bus_width == MMC_BUS_WIDTH_8)
+		clock <<= 1;
+
+	rate = clk_round_rate(host->clk_mmc, clock);
 	dev_dbg(mmc_dev(host->mmc), "setting clk to %d, rounded %d\n",
-		ios->clock, rate);
+		clock, rate);
 
 	/* setting clock rate */
 	ret = clk_set_rate(host->clk_mmc, rate);
@@ -677,6 +684,12 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
 	/* clear internal divider */
 	rval = mmc_readl(host, REG_CLKCR);
 	rval &= ~0xff;
+	/* set internal divider for 8 bit eMMC DDR, so card clock is right */
+	if (ios->timing == MMC_TIMING_MMC_DDR52 &&
+	    ios->bus_width == MMC_BUS_WIDTH_8) {
+		rval |= 1;
+		rate >>= 1;
+	}
 	mmc_writel(host, REG_CLKCR, rval);
 
 	/* determine delays */
@@ -687,13 +700,16 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
 		oclk_dly = host->clk_delays[SDXC_CLK_25M].output;
 		sclk_dly = host->clk_delays[SDXC_CLK_25M].sample;
 	} else if (rate <= 50000000) {
-		if (ios->timing == MMC_TIMING_UHS_DDR50 ||
-		    ios->timing == MMC_TIMING_MMC_DDR52) {
-			oclk_dly = host->clk_delays[SDXC_CLK_50M_DDR].output;
-			sclk_dly = host->clk_delays[SDXC_CLK_50M_DDR].sample;
-		} else {
+		if (ios->timing != MMC_TIMING_UHS_DDR50 &&
+		    ios->timing != MMC_TIMING_MMC_DDR52) {
 			oclk_dly = host->clk_delays[SDXC_CLK_50M].output;
 			sclk_dly = host->clk_delays[SDXC_CLK_50M].sample;
+		} else if (ios->bus_width == MMC_BUS_WIDTH_8) {
+			oclk_dly = host->clk_delays[SDXC_CLK_50M_DDR_8BIT].output;
+			sclk_dly = host->clk_delays[SDXC_CLK_50M_DDR_8BIT].sample;
+		} else {
+			oclk_dly = host->clk_delays[SDXC_CLK_50M_DDR].output;
+			sclk_dly = host->clk_delays[SDXC_CLK_50M_DDR].sample;
 		}
 	} else {
 		return -EINVAL;
@@ -965,6 +981,8 @@ static const struct sunxi_mmc_clk_delay sunxi_mmc_clk_delays[] = {
 	[SDXC_CLK_25M]		= { .output = 180, .sample =  75 },
 	[SDXC_CLK_50M]		= { .output =  90, .sample = 120 },
 	[SDXC_CLK_50M_DDR]	= { .output =  60, .sample = 120 },
+	/* Value from A83T "new timing mode". Works but might not be right. */
+	[SDXC_CLK_50M_DDR_8BIT]	= { .output =  90, .sample = 180 },
 };
 
 static const struct sunxi_mmc_clk_delay sun9i_mmc_clk_delays[] = {
@@ -972,6 +990,7 @@ static const struct sunxi_mmc_clk_delay sun9i_mmc_clk_delays[] = {
 	[SDXC_CLK_25M]		= { .output = 180, .sample =  75 },
 	[SDXC_CLK_50M]		= { .output = 150, .sample = 120 },
 	[SDXC_CLK_50M_DDR]	= { .output =  90, .sample = 120 },
+	[SDXC_CLK_50M_DDR_8BIT]	= { .output =  90, .sample = 120 },
 };
 
 static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host,
-- 
2.7.0.rc3

[PATCH RFC 07/15] mmc: sunxi: Enable eMMC HS-DDR (MMC_CAP_1_8V_DDR) support

[Chen-Yu Tsai]

Now that clock delay settings for 8 bit DDR are correct, and vqmmc
support is available, we can enable MMC_CAP_1_8V_DDR support. This
enables MMC HS-DDR at up to 52 MHz, even if signal voltage switching
is not available.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 drivers/mmc/host/sunxi-mmc.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
index d05928091b34..f3a7f36e38c2 100644
--- a/drivers/mmc/host/sunxi-mmc.c
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -1145,6 +1145,7 @@ static int sunxi_mmc_probe(struct platform_device *pdev)
 	mmc->f_min		=   400000;
 	mmc->f_max		= 50000000;
 	mmc->caps	       |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
+				  MMC_CAP_1_8V_DDR |
 				  MMC_CAP_ERASE | MMC_CAP_SDIO_IRQ;
 
 	ret = mmc_of_parse(mmc);
-- 
2.7.0.rc3

[PATCH RFC 08/15] ARM: dts: sun6i: Add mmc3 pins for 8 bit emmc

[Chen-Yu Tsai]

mmc2 and mmc3 are available on the same pins, with different mux values.
However, only mmc3 supports 8 bit DDR transfer modes.

Since preference for mmc3 over mmc2 is due to DDR transfer modes, just
set the drive strength to 40mA, which is needed for DDR.

This pinmux setting also includes the hardware reset pin for emmc.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun6i-a31.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index b6ad7850fac6..1867af24ff52 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -709,6 +709,16 @@
 				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 			};
 
+			mmc3_8bit_emmc_pins: mmc3@1 {
+				allwinner,pins = "PC6", "PC7", "PC8", "PC9",
+						 "PC10", "PC11", "PC12",
+						 "PC13", "PC14", "PC15",
+						 "PC24";
+				allwinner,function = "mmc3";
+				allwinner,drive = <SUN4I_PINCTRL_40_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
 			gmac_pins_mii_a: gmac_mii@0 {
 				allwinner,pins = "PA0", "PA1", "PA2", "PA3",
 						"PA8", "PA9", "PA11",
-- 
2.7.0.rc3

[PATCH RFC 09/15] ARM: dts: sun6i: sina31s: Switch to mmc3 for onboard eMMC

[Chen-Yu Tsai]

According to Allwinner, only mmc3 supports 8 bit DDR transfers for eMMC.
Switch to mmc3 for the onboard eMMC, and also assign vqmmc for signal
voltage sensing/switching, and "cap-mmc-hw-reset" to denote this
instance can use eMMC hardware reset.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi b/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
index ea69fb8ad4d8..4ec0c8679b2e 100644
--- a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
@@ -61,12 +61,14 @@
 };
 
 /* eMMC on core board */
-&mmc2 {
+&mmc3 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&mmc2_8bit_emmc_pins>;
+	pinctrl-0 = <&mmc3_8bit_emmc_pins>;
 	vmmc-supply = <&reg_dcdc1>;
+	vqmmc-supply = <&reg_dcdc1>;
 	bus-width = <8>;
 	non-removable;
+	cap-mmc-hw-reset;
 	status = "okay";
 };
 
-- 
2.7.0.rc3

[PATCH RFC 10/15] ARM: dts: sun8i: Include SDC2_RST pin in mmc2_8bit_pins

[Chen-Yu Tsai]

mmc2_8bit_pins is used with eMMC chips, which also have a reset pin.
The MMC controller also has a reset output that is supported.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun8i-a23-a33.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
index 6f88fb0ddbc7..7e05e09e61c7 100644
--- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
@@ -381,7 +381,7 @@
 				allwinner,pins = "PC5", "PC6", "PC8",
 						 "PC9", "PC10", "PC11",
 						 "PC12", "PC13", "PC14",
-						 "PC15";
+						 "PC15", "PC16";
 				allwinner,function = "mmc2";
 				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
-- 
2.7.0.rc3

[PATCH RFC 11/15] ARM: dts: sun8i: sina33: Enable hardware reset and HS-DDR for eMMC

[Chen-Yu Tsai]

mmc2 has a special pin for eMMC hardware reset, which is controllable
from the controller. Add the "mmc-cap-hw-reset" property to denote that
this controller supports this function, and the pins are actually used.

Also increase the signal drive strength for mmc2 pins, for HS-DDR mode
support.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
index 13ce68f06dd6..bd2a3beb4629 100644
--- a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
+++ b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
@@ -109,10 +109,13 @@
 	vmmc-supply = <&reg_vcc3v0>;
 	bus-width = <8>;
 	non-removable;
+	cap-mmc-hw-reset;
 	status = "okay";
 };
 
 &mmc2_8bit_pins {
+	/* Increase drive strength for DDR modes */
+	allwinner,drive = <SUN4I_PINCTRL_40_MA>;
 	/* eMMC is missing pull-ups */
 	allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
 };
-- 
2.7.0.rc3

[PATCH RFC 12/15] ARM: dts: sun9i: Use sun9i specific mmc compatible

[Chen-Yu Tsai]

sun9i/A80 MMC controllers have a larger FIFO, and the FIFO DMA
trigger levels can be increased. Also, the mmc module clock parent
has a higher clock rate, and the sample and output delay phases
are different.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun9i-a80.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index e838f206f2a0..f4f61b02be1a 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -543,7 +543,7 @@
 		};
 
 		mmc0: mmc@01c0f000 {
-			compatible = "allwinner,sun5i-a13-mmc";
+			compatible = "allwinner,sun9i-a80-mmc";
 			reg = <0x01c0f000 0x1000>;
 			clocks = <&mmc_config_clk 0>, <&mmc0_clk 0>,
 				 <&mmc0_clk 1>, <&mmc0_clk 2>;
@@ -557,7 +557,7 @@
 		};
 
 		mmc1: mmc@01c10000 {
-			compatible = "allwinner,sun5i-a13-mmc";
+			compatible = "allwinner,sun9i-a80-mmc";
 			reg = <0x01c10000 0x1000>;
 			clocks = <&mmc_config_clk 1>, <&mmc1_clk 0>,
 				 <&mmc1_clk 1>, <&mmc1_clk 2>;
@@ -571,7 +571,7 @@
 		};
 
 		mmc2: mmc@01c11000 {
-			compatible = "allwinner,sun5i-a13-mmc";
+			compatible = "allwinner,sun9i-a80-mmc";
 			reg = <0x01c11000 0x1000>;
 			clocks = <&mmc_config_clk 2>, <&mmc2_clk 0>,
 				 <&mmc2_clk 1>, <&mmc2_clk 2>;
@@ -585,7 +585,7 @@
 		};
 
 		mmc3: mmc@01c12000 {
-			compatible = "allwinner,sun5i-a13-mmc";
+			compatible = "allwinner,sun9i-a80-mmc";
 			reg = <0x01c12000 0x1000>;
 			clocks = <&mmc_config_clk 3>, <&mmc3_clk 0>,
 				 <&mmc3_clk 1>, <&mmc3_clk 2>;
-- 
2.7.0.rc3

[PATCH RFC 13/15] ARM: dts: sun9i: Include SDC2_RST pin in mmc2_8bit_pins

[Chen-Yu Tsai]

mmc2_8bit_pins is used with eMMC chips, which also have a reset pin.
The MMC controller also has a reset output that is supported.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun9i-a80.dtsi | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index f4f61b02be1a..f68b3242b33a 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -704,7 +704,8 @@
 			mmc2_8bit_pins: mmc2_8bit {
 				allwinner,pins = "PC6", "PC7", "PC8", "PC9",
 						 "PC10", "PC11", "PC12",
-						 "PC13", "PC14", "PC15";
+						 "PC13", "PC14", "PC15",
+						 "PC16";
 				allwinner,function = "mmc2";
 				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
-- 
2.7.0.rc3

[PATCH RFC 14/15] ARM: dts: sun9i: a80-optimus: Enable hardware reset and HS-DDR for eMMC

[Chen-Yu Tsai]

mmc2 has a special pin for eMMC hardware reset, which is controllable
from the controller. Add the "mmc-cap-hw-reset" property to denote that
this controller supports this function, and the pins are actually used.

Also increase the signal drive strength for mmc2 pins, for HS-DDR mode
support.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun9i-a80-optimus.dts | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/sun9i-a80-optimus.dts
index c0060e4f7379..958160e40fd0 100644
--- a/arch/arm/boot/dts/sun9i-a80-optimus.dts
+++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts
@@ -174,9 +174,15 @@
 	vmmc-supply = <&reg_vcc3v0>;
 	bus-width = <8>;
 	non-removable;
+	cap-mmc-hw-reset;
 	status = "okay";
 };
 
+&mmc2_8bit_pins {
+	/* Increase drive strength for DDR modes */
+	allwinner,drive = <SUN4I_PINCTRL_40_MA>;
+};
+
 &reg_usb1_vbus {
 	pinctrl-0 = <&usb1_vbus_pin_optimus>;
 	gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
-- 
2.7.0.rc3

[PATCH RFC 15/15] ARM: dts: sun9i: cubieboard4: Enable hardware reset and HS-DDR for eMMC

[Chen-Yu Tsai]

mmc2 has a special pin for eMMC hardware reset, which is controllable
from the controller. Add the "mmc-cap-hw-reset" property to denote that
this controller supports this function, and the pins are actually used.

Also increase the signal drive strength for mmc2 pins, for HS-DDR mode
support.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun9i-a80-cubieboard4.dts | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
index 382bd9fc5647..eb2ccd0a3bd5 100644
--- a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
+++ b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
@@ -111,9 +111,15 @@
 	vmmc-supply = <&reg_vcc3v0>;
 	bus-width = <8>;
 	non-removable;
+	cap-mmc-hw-reset;
 	status = "okay";
 };
 
+&mmc2_8bit_pins {
+	/* Increase drive strength for DDR modes */
+	allwinner,drive = <SUN4I_PINCTRL_40_MA>;
+};
+
 &r_ir {
 	status = "okay";
 };
-- 
2.7.0.rc3

Re: [PATCH RFC 05/15] mmc: sunxi: Support MMC_DDR52 timing modes

[Hans de Goede]

Hi,

On 21-01-16 06:26, Chen-Yu Tsai wrote:
> DDR transfer modes include UHS-1 DDR50 and MMC HS-DDR (or MMC_DDR52).
> Consider MMC_DDR52 when setting clock delays.
>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
>   drivers/mmc/host/sunxi-mmc.c | 6 ++++--
>   1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
> index 4bec87458317..b403a2433eec 100644
> --- a/drivers/mmc/host/sunxi-mmc.c
> +++ b/drivers/mmc/host/sunxi-mmc.c
> @@ -687,7 +687,8 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
>   		oclk_dly = host->clk_delays[SDXC_CLK_25M].output;
>   		sclk_dly = host->clk_delays[SDXC_CLK_25M].sample;
>   	} else if (rate <= 50000000) {

Shouldn't this be <= 52000000 then, considering that we may at one point get
some PLL setup where we may actually be able to do 52000000 for MMC_TIMING_MMC_DDR52 ?

> -		if (ios->timing == MMC_TIMING_UHS_DDR50) {
> +		if (ios->timing == MMC_TIMING_UHS_DDR50 ||
> +		    ios->timing == MMC_TIMING_MMC_DDR52) {
>   			oclk_dly = host->clk_delays[SDXC_CLK_50M_DDR].output;
>   			sclk_dly = host->clk_delays[SDXC_CLK_50M_DDR].sample;
>   		} else {
> @@ -762,7 +763,8 @@ static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
>
>   	/* set ddr mode */
>   	rval = mmc_readl(host, REG_GCTRL);
> -	if (ios->timing == MMC_TIMING_UHS_DDR50)
> +	if (ios->timing == MMC_TIMING_UHS_DDR50 ||
> +	    ios->timing == MMC_TIMING_MMC_DDR52)
>   		rval |= SDXC_DDR_MODE;
>   	else
>   		rval &= ~SDXC_DDR_MODE;
>

Regards,

Hans

Re: [PATCH RFC 09/15] ARM: dts: sun6i: sina31s: Switch to mmc3 for onboard eMMC

[Hans de Goede]

Hi,

On 21-01-16 06:26, Chen-Yu Tsai wrote:
> According to Allwinner, only mmc3 supports 8 bit DDR transfers for eMMC.
> Switch to mmc3 for the onboard eMMC, and also assign vqmmc for signal
> voltage sensing/switching, and "cap-mmc-hw-reset" to denote this
> instance can use eMMC hardware reset.

This is going to need some more explanation, does this mean
that the old dtsi is wrong and the emmc does not work there are all ?

Regards,

Hans


>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
>   arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi | 6 ++++--
>   1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi b/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
> index ea69fb8ad4d8..4ec0c8679b2e 100644
> --- a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
> +++ b/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
> @@ -61,12 +61,14 @@
>   };
>
>   /* eMMC on core board */
> -&mmc2 {
> +&mmc3 {
>   	pinctrl-names = "default";
> -	pinctrl-0 = <&mmc2_8bit_emmc_pins>;
> +	pinctrl-0 = <&mmc3_8bit_emmc_pins>;
>   	vmmc-supply = <&reg_dcdc1>;
> +	vqmmc-supply = <&reg_dcdc1>;
>   	bus-width = <8>;
>   	non-removable;
> +	cap-mmc-hw-reset;
>   	status = "okay";
>   };
>
>

Re: [PATCH RFC 00/15] mmc: sunxi: Support vqmmc regulator and eMMC DDR modes

[Hans de Goede]

Hi,

On 21-01-16 06:26, Chen-Yu Tsai wrote:
> Hi everyone,
>
> This series adds support for vqmmc regulator and eMMC DDR modes for
> sunxi-mmc. Allwinner's MMC controller supports eMMC 4.41 on earlier
> SoCs, and up to 5.0 on latest ones. UHS-1 modes are also supported
> by the hardware, but these are not covered in this series, as no
> boards have dedicated regulators for vqmmc.
>
> To support these faster modes, these patches adds vqmmc regulator
> support, which is used by the mmc core to switch to faster modes,
> even if the signaling voltage is fixed. Signal voltage switching
> support is also added, but not tested, as no available hardware has
> a dedicated vqmmc regulator.
>
> Support for eMMC reset in the controller, vs a GPIO and pwrseq, is
> also added where applicable.

Thanks for working on this. I've send my remarks to a few of the patches,
the ones I've not remarked on look good to me.

Regards,

Hans


>
> Patch 1 documents the mmc host init sequence. When the driver was
> ported, this part was copied verbatim and not documented. With inline
> comments from later SDKs and datasheet register definitions, this part
> is now clearer.
>
> Patch 2 makes the .set_ios callback return on errors from
> mmc_regulator_set_ocr.
>
> Patch 3 adds support (enabling/disable, and voltage control) for vqmmc
> regulator to sunxi-mmc.
>
> Patch 4 adds support signal voltage switch for the mmc controller. The
> Allwinner MMC controller uses a special bit for sending signal voltage
> switching command.
>
> Patch 5 adds timing delays for MMC_DDR52 mode.
>
> Patch 6 adds support for 8 bit eMMC DDR52 mode. Under this mode, the
> controller must run at twice the card clock, and different timing delays
> are needed.
>
> Patch 7 enables eMMC HS-DDR for sunxi-mmc.
>
> Patch 8 adds mmc3 pins for 8 bit emmc for A31/A31s.
>
> Patch 9 switches from mmc2 to mmc3 for the onboard eMMC on Sinlinx
> SinA31s. According to Allwinner, only mmc3 supports eMMC DDR52 on
> A31/A31s.
>
> Patch 10 adds the eMMC reset pin to the emmc pingroup for A23/A33.
>
> Patch 11 enables eMMC hardware reset and eMMC DDR52 mode for SinA33.
>
> Patch 12 switches A80 to sun9i specific mmc compatible. A80 has different
> timing delays, and a larger FIFO (TODO).
>
> Patch 13 adds the eMMC reset pin to the emmc pingroup for A80.
>
> Patch 14 enables eMMC hardware reset and eMMC DDR52 mode for A80 Optimus.
>
> Patch 15 enables eMMC hardware reset and eMMC DDR52 mode for Cubieboard4.
>
> Chen-Yu Tsai (15):
>    mmc: sunxi: Document host init sequence
>    mmc: sunxi: Return error on mmc_regulator_set_ocr() fail in .set_ios
>      op
>    mmc: sunxi: Block signal voltage switching (CMD11)
>    mmc: sunxi: Support vqmmc regulator
>    mmc: sunxi: Support MMC_DDR52 timing modes
>    mmc: sunxi: Support 8 bit eMMC DDR transfer modes
>    mmc: sunxi: Enable eMMC HS-DDR (MMC_CAP_1_8V_DDR) support
>    ARM: dts: sun6i: Add mmc3 pins for 8 bit emmc
>    ARM: dts: sun6i: sina31s: Switch to mmc3 for onboard eMMC
>    ARM: dts: sun8i: Include SDC2_RST pin in mmc2_8bit_pins
>    ARM: dts: sun8i: sina33: Enable hardware reset and HS-DDR for eMMC
>    ARM: dts: sun9i: Use sun9i specific mmc compatible
>    ARM: dts: sun9i: Include SDC2_RST pin in mmc2_8bit_pins
>    ARM: dts: sun9i: a80-optimus: Enable hardware reset and HS-DDR for
>      eMMC
>    ARM: dts: sun9i: cubieboard4: Enable hardware reset and HS-DDR for
>      eMMC
>
>   arch/arm/boot/dts/sun6i-a31.dtsi               | 10 +++
>   arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi |  6 +-
>   arch/arm/boot/dts/sun8i-a23-a33.dtsi           |  2 +-
>   arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts |  3 +
>   arch/arm/boot/dts/sun9i-a80-cubieboard4.dts    |  6 ++
>   arch/arm/boot/dts/sun9i-a80-optimus.dts        |  6 ++
>   arch/arm/boot/dts/sun9i-a80.dtsi               | 11 +--
>   drivers/mmc/host/sunxi-mmc.c                   | 98 +++++++++++++++++++++++---
>   8 files changed, 126 insertions(+), 16 deletions(-)
>

Re: [PATCH RFC 05/15] mmc: sunxi: Support MMC_DDR52 timing modes

[Chen-Yu Tsai]

On Thu, Jan 21, 2016 at 7:14 PM, Hans de Goede <hdegoede@redhat.com> wrote:
> Hi,
>
> On 21-01-16 06:26, Chen-Yu Tsai wrote:
>>
>> DDR transfer modes include UHS-1 DDR50 and MMC HS-DDR (or MMC_DDR52).
>> Consider MMC_DDR52 when setting clock delays.
>>
>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>> ---
>>   drivers/mmc/host/sunxi-mmc.c | 6 ++++--
>>   1 file changed, 4 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
>> index 4bec87458317..b403a2433eec 100644
>> --- a/drivers/mmc/host/sunxi-mmc.c
>> +++ b/drivers/mmc/host/sunxi-mmc.c
>> @@ -687,7 +687,8 @@ static int sunxi_mmc_clk_set_rate(struct
>> sunxi_mmc_host *host,
>>                 oclk_dly = host->clk_delays[SDXC_CLK_25M].output;
>>                 sclk_dly = host->clk_delays[SDXC_CLK_25M].sample;
>>         } else if (rate <= 50000000) {
>
>
> Shouldn't this be <= 52000000 then, considering that we may at one point get
> some PLL setup where we may actually be able to do 52000000 for
> MMC_TIMING_MMC_DDR52 ?

Given that mmc->f_max = 50000000, the core will never try any clock rate higher
than 50 MHz, and iirc clk_round_rate always rounds down. We could increase both
numbers at the same time when we actually encounter such hardware.

Or we could increase both now, which I actually did in an earlier version, but
it really made no difference with current hardware.


Regards
ChenYu

>
>> -               if (ios->timing == MMC_TIMING_UHS_DDR50) {
>> +               if (ios->timing == MMC_TIMING_UHS_DDR50 ||
>> +                   ios->timing == MMC_TIMING_MMC_DDR52) {
>>                         oclk_dly =
>> host->clk_delays[SDXC_CLK_50M_DDR].output;
>>                         sclk_dly =
>> host->clk_delays[SDXC_CLK_50M_DDR].sample;
>>                 } else {
>> @@ -762,7 +763,8 @@ static void sunxi_mmc_set_ios(struct mmc_host *mmc,
>> struct mmc_ios *ios)
>>
>>         /* set ddr mode */
>>         rval = mmc_readl(host, REG_GCTRL);
>> -       if (ios->timing == MMC_TIMING_UHS_DDR50)
>> +       if (ios->timing == MMC_TIMING_UHS_DDR50 ||
>> +           ios->timing == MMC_TIMING_MMC_DDR52)
>>                 rval |= SDXC_DDR_MODE;
>>         else
>>                 rval &= ~SDXC_DDR_MODE;
>>
>
> Regards,
>
> Hans

Re: [PATCH RFC 09/15] ARM: dts: sun6i: sina31s: Switch to mmc3 for onboard eMMC

[Chen-Yu Tsai]

On Thu, Jan 21, 2016 at 7:16 PM, Hans de Goede <hdegoede@redhat.com> wrote:
> Hi,
>
> On 21-01-16 06:26, Chen-Yu Tsai wrote:
>>
>> According to Allwinner, only mmc3 supports 8 bit DDR transfers for eMMC.
>> Switch to mmc3 for the onboard eMMC, and also assign vqmmc for signal
>> voltage sensing/switching, and "cap-mmc-hw-reset" to denote this
>> instance can use eMMC hardware reset.
>
>
> This is going to need some more explanation, does this mean
> that the old dtsi is wrong and the emmc does not work there are all ?

mmc2 works fine for either 4 bit SDR/DDR or 8 bit SDR only. It does
not work for 8 bit DDR. I actually tested all the above combinations.

Also see https://groups.google.com/d/msg/linux-sunxi/pMzwMWwLALw/6WGgCN1eAQAJ

About old DTs not working:

a) The old DT will not work with the mmc patches, as it will try 8 bit DDR
   and fail. Also, the old DT does not use the highest drive strength for
   the mmc pins, meaning it might not work for the other chip families.

b) Old DT + old kernel works fine (8 bit high-speed), just slower.

An alternative would be to drop MMC_CAP_1_8V_DDR from the driver, and
use the "mmc-ddr-1_8v" DT capability flag at the dtsi or board level.
There's no real way to describe "don't use 8 bit with MMC DDR" in the DT.


Regards
ChenYu

>
> Regards,
>
> Hans
>
>
>
>>
>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>> ---
>>   arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi | 6 ++++--
>>   1 file changed, 4 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
>> b/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
>> index ea69fb8ad4d8..4ec0c8679b2e 100644
>> --- a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
>> +++ b/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
>> @@ -61,12 +61,14 @@
>>   };
>>
>>   /* eMMC on core board */
>> -&mmc2 {
>> +&mmc3 {
>>         pinctrl-names = "default";
>> -       pinctrl-0 = <&mmc2_8bit_emmc_pins>;
>> +       pinctrl-0 = <&mmc3_8bit_emmc_pins>;
>>         vmmc-supply = <&reg_dcdc1>;
>> +       vqmmc-supply = <&reg_dcdc1>;
>>         bus-width = <8>;
>>         non-removable;
>> +       cap-mmc-hw-reset;
>>         status = "okay";
>>   };
>>
>>
>

Re: [PATCH RFC 09/15] ARM: dts: sun6i: sina31s: Switch to mmc3 for onboard eMMC

[Hans de Goede]

Hi,

On 21-01-16 13:23, Chen-Yu Tsai wrote:
> On Thu, Jan 21, 2016 at 7:16 PM, Hans de Goede <hdegoede@redhat.com> wrote:
>> Hi,
>>
>> On 21-01-16 06:26, Chen-Yu Tsai wrote:
>>>
>>> According to Allwinner, only mmc3 supports 8 bit DDR transfers for eMMC.
>>> Switch to mmc3 for the onboard eMMC, and also assign vqmmc for signal
>>> voltage sensing/switching, and "cap-mmc-hw-reset" to denote this
>>> instance can use eMMC hardware reset.
>>
>>
>> This is going to need some more explanation, does this mean
>> that the old dtsi is wrong and the emmc does not work there are all ?
>
> mmc2 works fine for either 4 bit SDR/DDR or 8 bit SDR only. It does
> not work for 8 bit DDR. I actually tested all the above combinations.
>
> Also see https://groups.google.com/d/msg/linux-sunxi/pMzwMWwLALw/6WGgCN1eAQAJ
>
> About old DTs not working:
>
> a) The old DT will not work with the mmc patches, as it will try 8 bit DDR
>     and fail. Also, the old DT does not use the highest drive strength for
>     the mmc pins, meaning it might not work for the other chip families.
>
> b) Old DT + old kernel works fine (8 bit high-speed), just slower.
>
> An alternative would be to drop MMC_CAP_1_8V_DDR from the driver, and
> use the "mmc-ddr-1_8v" DT capability flag at the dtsi or board level.
> There's no real way to describe "don't use 8 bit with MMC DDR" in the DT.

OK, so what is confusing me, is how can we choose between the emmc being
connected to mmc2 resp mmc3, are there dipswitches on the board? Or can both
mmc controllers be routed to the outside on the same port/pins ?

Regards,

Hans


>
>
> Regards
> ChenYu
>
>>
>> Regards,
>>
>> Hans
>>
>>
>>
>>>
>>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>>> ---
>>>    arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi | 6 ++++--
>>>    1 file changed, 4 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
>>> b/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
>>> index ea69fb8ad4d8..4ec0c8679b2e 100644
>>> --- a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
>>> +++ b/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
>>> @@ -61,12 +61,14 @@
>>>    };
>>>
>>>    /* eMMC on core board */
>>> -&mmc2 {
>>> +&mmc3 {
>>>          pinctrl-names = "default";
>>> -       pinctrl-0 = <&mmc2_8bit_emmc_pins>;
>>> +       pinctrl-0 = <&mmc3_8bit_emmc_pins>;
>>>          vmmc-supply = <&reg_dcdc1>;
>>> +       vqmmc-supply = <&reg_dcdc1>;
>>>          bus-width = <8>;
>>>          non-removable;
>>> +       cap-mmc-hw-reset;
>>>          status = "okay";
>>>    };
>>>
>>>
>>

Re: [PATCH RFC 05/15] mmc: sunxi: Support MMC_DDR52 timing modes

[Hans de Goede]

Hi,

On 21-01-16 12:55, Chen-Yu Tsai wrote:
> On Thu, Jan 21, 2016 at 7:14 PM, Hans de Goede <hdegoede@redhat.com> wrote:
>> Hi,
>>
>> On 21-01-16 06:26, Chen-Yu Tsai wrote:
>>>
>>> DDR transfer modes include UHS-1 DDR50 and MMC HS-DDR (or MMC_DDR52).
>>> Consider MMC_DDR52 when setting clock delays.
>>>
>>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>>> ---
>>>    drivers/mmc/host/sunxi-mmc.c | 6 ++++--
>>>    1 file changed, 4 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
>>> index 4bec87458317..b403a2433eec 100644
>>> --- a/drivers/mmc/host/sunxi-mmc.c
>>> +++ b/drivers/mmc/host/sunxi-mmc.c
>>> @@ -687,7 +687,8 @@ static int sunxi_mmc_clk_set_rate(struct
>>> sunxi_mmc_host *host,
>>>                  oclk_dly = host->clk_delays[SDXC_CLK_25M].output;
>>>                  sclk_dly = host->clk_delays[SDXC_CLK_25M].sample;
>>>          } else if (rate <= 50000000) {
>>
>>
>> Shouldn't this be <= 52000000 then, considering that we may at one point get
>> some PLL setup where we may actually be able to do 52000000 for
>> MMC_TIMING_MMC_DDR52 ?
>
> Given that mmc->f_max = 50000000, the core will never try any clock rate higher
> than 50 MHz, and iirc clk_round_rate always rounds down. We could increase both
> numbers at the same time when we actually encounter such hardware.

I'm afraid that someone may increase mmc->f_max = 50000000 at one point without
adjusting the rate checks above at the same time, so lets update both of them now.

Regards,

Hans

Re: [PATCH RFC 09/15] ARM: dts: sun6i: sina31s: Switch to mmc3 for onboard eMMC

[Chen-Yu Tsai]

On Thu, Jan 21, 2016 at 8:25 PM, Hans de Goede <hdegoede@redhat.com> wrote:
> Hi,
>
> On 21-01-16 13:23, Chen-Yu Tsai wrote:
>>
>> On Thu, Jan 21, 2016 at 7:16 PM, Hans de Goede <hdegoede@redhat.com>
>> wrote:
>>>
>>> Hi,
>>>
>>> On 21-01-16 06:26, Chen-Yu Tsai wrote:
>>>>
>>>>
>>>> According to Allwinner, only mmc3 supports 8 bit DDR transfers for eMMC.
>>>> Switch to mmc3 for the onboard eMMC, and also assign vqmmc for signal
>>>> voltage sensing/switching, and "cap-mmc-hw-reset" to denote this
>>>> instance can use eMMC hardware reset.
>>>
>>>
>>>
>>> This is going to need some more explanation, does this mean
>>> that the old dtsi is wrong and the emmc does not work there are all ?
>>
>>
>> mmc2 works fine for either 4 bit SDR/DDR or 8 bit SDR only. It does
>> not work for 8 bit DDR. I actually tested all the above combinations.
>>
>> Also see
>> https://groups.google.com/d/msg/linux-sunxi/pMzwMWwLALw/6WGgCN1eAQAJ
>>
>> About old DTs not working:
>>
>> a) The old DT will not work with the mmc patches, as it will try 8 bit DDR
>>     and fail. Also, the old DT does not use the highest drive strength for
>>     the mmc pins, meaning it might not work for the other chip families.
>>
>> b) Old DT + old kernel works fine (8 bit high-speed), just slower.
>>
>> An alternative would be to drop MMC_CAP_1_8V_DDR from the driver, and
>> use the "mmc-ddr-1_8v" DT capability flag at the dtsi or board level.
>> There's no real way to describe "don't use 8 bit with MMC DDR" in the DT.
>
>
> OK, so what is confusing me, is how can we choose between the emmc being
> connected to mmc2 resp mmc3, are there dipswitches on the board? Or can both
> mmc controllers be routed to the outside on the same port/pins ?

They are on the same pins, just with a different mux value/function.
I believe the previous patch explains this.

ChenYu

>
> Regards,
>
> Hans
>
>
>
>>
>>
>> Regards
>> ChenYu
>>
>>>
>>> Regards,
>>>
>>> Hans
>>>
>>>
>>>
>>>>
>>>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>>>> ---
>>>>    arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi | 6 ++++--
>>>>    1 file changed, 4 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
>>>> b/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
>>>> index ea69fb8ad4d8..4ec0c8679b2e 100644
>>>> --- a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
>>>> +++ b/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
>>>> @@ -61,12 +61,14 @@
>>>>    };
>>>>
>>>>    /* eMMC on core board */
>>>> -&mmc2 {
>>>> +&mmc3 {
>>>>          pinctrl-names = "default";
>>>> -       pinctrl-0 = <&mmc2_8bit_emmc_pins>;
>>>> +       pinctrl-0 = <&mmc3_8bit_emmc_pins>;
>>>>          vmmc-supply = <&reg_dcdc1>;
>>>> +       vqmmc-supply = <&reg_dcdc1>;
>>>>          bus-width = <8>;
>>>>          non-removable;
>>>> +       cap-mmc-hw-reset;
>>>>          status = "okay";
>>>>    };
>>>>
>>>>
>>>
>

Re: [PATCH RFC 09/15] ARM: dts: sun6i: sina31s: Switch to mmc3 for onboard eMMC

[Hans de Goede]

Hi,

On 21-01-16 13:28, Chen-Yu Tsai wrote:
> On Thu, Jan 21, 2016 at 8:25 PM, Hans de Goede <hdegoede@redhat.com> wrote:
>> Hi,
>>
>> On 21-01-16 13:23, Chen-Yu Tsai wrote:
>>>
>>> On Thu, Jan 21, 2016 at 7:16 PM, Hans de Goede <hdegoede@redhat.com>
>>> wrote:
>>>>
>>>> Hi,
>>>>
>>>> On 21-01-16 06:26, Chen-Yu Tsai wrote:
>>>>>
>>>>>
>>>>> According to Allwinner, only mmc3 supports 8 bit DDR transfers for eMMC.
>>>>> Switch to mmc3 for the onboard eMMC, and also assign vqmmc for signal
>>>>> voltage sensing/switching, and "cap-mmc-hw-reset" to denote this
>>>>> instance can use eMMC hardware reset.
>>>>
>>>>
>>>>
>>>> This is going to need some more explanation, does this mean
>>>> that the old dtsi is wrong and the emmc does not work there are all ?
>>>
>>>
>>> mmc2 works fine for either 4 bit SDR/DDR or 8 bit SDR only. It does
>>> not work for 8 bit DDR. I actually tested all the above combinations.
>>>
>>> Also see
>>> https://groups.google.com/d/msg/linux-sunxi/pMzwMWwLALw/6WGgCN1eAQAJ
>>>
>>> About old DTs not working:
>>>
>>> a) The old DT will not work with the mmc patches, as it will try 8 bit DDR
>>>      and fail. Also, the old DT does not use the highest drive strength for
>>>      the mmc pins, meaning it might not work for the other chip families.
>>>
>>> b) Old DT + old kernel works fine (8 bit high-speed), just slower.
>>>
>>> An alternative would be to drop MMC_CAP_1_8V_DDR from the driver, and
>>> use the "mmc-ddr-1_8v" DT capability flag at the dtsi or board level.
>>> There's no real way to describe "don't use 8 bit with MMC DDR" in the DT.
>>
>>
>> OK, so what is confusing me, is how can we choose between the emmc being
>> connected to mmc2 resp mmc3, are there dipswitches on the board? Or can both
>> mmc controllers be routed to the outside on the same port/pins ?
>
> They are on the same pins, just with a different mux value/function.
> I believe the previous patch explains this.

Ah yes, I see the remark about them sharing pins in the previous
patch commit msg now, weird.

Regards,

Hans


>
> ChenYu
>
>>
>> Regards,
>>
>> Hans
>>
>>
>>
>>>
>>>
>>> Regards
>>> ChenYu
>>>
>>>>
>>>> Regards,
>>>>
>>>> Hans
>>>>
>>>>
>>>>
>>>>>
>>>>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>>>>> ---
>>>>>     arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi | 6 ++++--
>>>>>     1 file changed, 4 insertions(+), 2 deletions(-)
>>>>>
>>>>> diff --git a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
>>>>> b/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
>>>>> index ea69fb8ad4d8..4ec0c8679b2e 100644
>>>>> --- a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
>>>>> +++ b/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
>>>>> @@ -61,12 +61,14 @@
>>>>>     };
>>>>>
>>>>>     /* eMMC on core board */
>>>>> -&mmc2 {
>>>>> +&mmc3 {
>>>>>           pinctrl-names = "default";
>>>>> -       pinctrl-0 = <&mmc2_8bit_emmc_pins>;
>>>>> +       pinctrl-0 = <&mmc3_8bit_emmc_pins>;
>>>>>           vmmc-supply = <&reg_dcdc1>;
>>>>> +       vqmmc-supply = <&reg_dcdc1>;
>>>>>           bus-width = <8>;
>>>>>           non-removable;
>>>>> +       cap-mmc-hw-reset;
>>>>>           status = "okay";
>>>>>     };
>>>>>
>>>>>
>>>>
>>

Re: [PATCH RFC 08/15] ARM: dts: sun6i: Add mmc3 pins for 8 bit emmc

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 1550 bytes --]

Hi, 

On Thu, Jan 21, 2016 at 01:26:35PM +0800, Chen-Yu Tsai wrote:
> mmc2 and mmc3 are available on the same pins, with different mux values.
> However, only mmc3 supports 8 bit DDR transfer modes.
> 
> Since preference for mmc3 over mmc2 is due to DDR transfer modes, just
> set the drive strength to 40mA, which is needed for DDR.
> 
> This pinmux setting also includes the hardware reset pin for emmc.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
>  arch/arm/boot/dts/sun6i-a31.dtsi | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
> index b6ad7850fac6..1867af24ff52 100644
> --- a/arch/arm/boot/dts/sun6i-a31.dtsi
> +++ b/arch/arm/boot/dts/sun6i-a31.dtsi
> @@ -709,6 +709,16 @@
>  				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>  			};
>  
> +			mmc3_8bit_emmc_pins: mmc3@1 {
> +				allwinner,pins = "PC6", "PC7", "PC8", "PC9",
> +						 "PC10", "PC11", "PC12",
> +						 "PC13", "PC14", "PC15",
> +						 "PC24";
> +				allwinner,function = "mmc3";
> +				allwinner,drive = <SUN4I_PINCTRL_40_MA>;
> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> +			};
> +

Is that reset pin optional?

If so, I'd prefer it to be a separate node, like we're doing for the
SPI chip selects for example.

It allows more reusability between different devices without declaring
new nodes.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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Re: [PATCH RFC 09/15] ARM: dts: sun6i: sina31s: Switch to mmc3 for onboard eMMC

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 1404 bytes --]

Hi,

On Thu, Jan 21, 2016 at 01:26:36PM +0800, Chen-Yu Tsai wrote:
> According to Allwinner, only mmc3 supports 8 bit DDR transfers for eMMC.
> Switch to mmc3 for the onboard eMMC, and also assign vqmmc for signal
> voltage sensing/switching, and "cap-mmc-hw-reset" to denote this
> instance can use eMMC hardware reset.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
>  arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi b/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
> index ea69fb8ad4d8..4ec0c8679b2e 100644
> --- a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
> +++ b/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
> @@ -61,12 +61,14 @@
>  };
>  
>  /* eMMC on core board */
> -&mmc2 {
> +&mmc3 {
>  	pinctrl-names = "default";
> -	pinctrl-0 = <&mmc2_8bit_emmc_pins>;
> +	pinctrl-0 = <&mmc3_8bit_emmc_pins>;
>  	vmmc-supply = <&reg_dcdc1>;
> +	vqmmc-supply = <&reg_dcdc1>;

That seems odd. IIRC the VCC was supposed to be fixed and VCCQ could
be either at 1.8 or 3V. Having the same regulator on both would make
VCCQ forced to 3.3V, which seems to go against your commit log.

What's the catch ? :)

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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Re: [PATCH RFC 11/15] ARM: dts: sun8i: sina33: Enable hardware reset and HS-DDR for eMMC

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 570 bytes --]

On Thu, Jan 21, 2016 at 01:26:38PM +0800, Chen-Yu Tsai wrote:
> mmc2 has a special pin for eMMC hardware reset, which is controllable
> from the controller. Add the "mmc-cap-hw-reset" property to denote that
> this controller supports this function, and the pins are actually used.
> 
> Also increase the signal drive strength for mmc2 pins, for HS-DDR mode
> support.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

Applied, thanks!

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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Re: [PATCH RFC 12/15] ARM: dts: sun9i: Use sun9i specific mmc compatible

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 570 bytes --]

On Thu, Jan 21, 2016 at 01:26:39PM +0800, Chen-Yu Tsai wrote:
> sun9i/A80 MMC controllers have a larger FIFO, and the FIFO DMA
> trigger levels can be increased. Also, the mmc module clock parent
> has a higher clock rate, and the sample and output delay phases
> are different.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

Applied, thanks!

Does that count as a fix, or does the A80 board can safely operate
without it?

Thanks,
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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Re: [PATCH RFC 09/15] ARM: dts: sun6i: sina31s: Switch to mmc3 for onboard eMMC

[Chen-Yu Tsai]

On Sat, Jan 23, 2016 at 4:39 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Hi,
>
> On Thu, Jan 21, 2016 at 01:26:36PM +0800, Chen-Yu Tsai wrote:
>> According to Allwinner, only mmc3 supports 8 bit DDR transfers for eMMC.
>> Switch to mmc3 for the onboard eMMC, and also assign vqmmc for signal
>> voltage sensing/switching, and "cap-mmc-hw-reset" to denote this
>> instance can use eMMC hardware reset.
>>
>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>> ---
>>  arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi | 6 ++++--
>>  1 file changed, 4 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi b/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
>> index ea69fb8ad4d8..4ec0c8679b2e 100644
>> --- a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
>> +++ b/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
>> @@ -61,12 +61,14 @@
>>  };
>>
>>  /* eMMC on core board */
>> -&mmc2 {
>> +&mmc3 {
>>       pinctrl-names = "default";
>> -     pinctrl-0 = <&mmc2_8bit_emmc_pins>;
>> +     pinctrl-0 = <&mmc3_8bit_emmc_pins>;
>>       vmmc-supply = <&reg_dcdc1>;
>> +     vqmmc-supply = <&reg_dcdc1>;
>
> That seems odd. IIRC the VCC was supposed to be fixed and VCCQ could
> be either at 1.8 or 3V. Having the same regulator on both would make
> VCCQ forced to 3.3V, which seems to go against your commit log.
>
> What's the catch ? :)

That is how the board is routed. Which means the only use for
vqmmc-supply is the driver will know that it can only do 3.3V,
i.e. voltage sensing.

It is the reason I requested Olimex to look into this. Allwinner
reference designs all tie vqmmc directly to 3.3V.

Actually with the latest driver patches, this is not even needed. To
make the driver backward compatible, if no vqmmc-supply is given, it
just assumes 3.3V signaling.

Regards
ChenYu

Re: [PATCH RFC 12/15] ARM: dts: sun9i: Use sun9i specific mmc compatible

[Chen-Yu Tsai]

On Sat, Jan 23, 2016 at 4:44 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> On Thu, Jan 21, 2016 at 01:26:39PM +0800, Chen-Yu Tsai wrote:
>> sun9i/A80 MMC controllers have a larger FIFO, and the FIFO DMA
>> trigger levels can be increased. Also, the mmc module clock parent
>> has a higher clock rate, and the sample and output delay phases
>> are different.
>>
>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>
> Applied, thanks!
>
> Does that count as a fix, or does the A80 board can safely operate
> without it?

The compatible was added in v4.3, in commit 51424b286067 ("mmc:
sunxi: Fix clk-delay settings").

I've not tested using the old compatibles with 50/52 MHz DDR. They
do work just fine with the transfer modes we already supported.

Either way its been there for a while so i don't see any need to
pick it out as a fix.

ChenYu

Re: [PATCH RFC 08/15] ARM: dts: sun6i: Add mmc3 pins for 8 bit emmc

[Chen-Yu Tsai]

Hi,

On Sat, Jan 23, 2016 at 4:31 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Hi,
>
> On Thu, Jan 21, 2016 at 01:26:35PM +0800, Chen-Yu Tsai wrote:
>> mmc2 and mmc3 are available on the same pins, with different mux values.
>> However, only mmc3 supports 8 bit DDR transfer modes.
>>
>> Since preference for mmc3 over mmc2 is due to DDR transfer modes, just
>> set the drive strength to 40mA, which is needed for DDR.
>>
>> This pinmux setting also includes the hardware reset pin for emmc.
>>
>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>> ---
>>  arch/arm/boot/dts/sun6i-a31.dtsi | 10 ++++++++++
>>  1 file changed, 10 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
>> index b6ad7850fac6..1867af24ff52 100644
>> --- a/arch/arm/boot/dts/sun6i-a31.dtsi
>> +++ b/arch/arm/boot/dts/sun6i-a31.dtsi
>> @@ -709,6 +709,16 @@
>>                               allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>>                       };
>>
>> +                     mmc3_8bit_emmc_pins: mmc3@1 {
>> +                             allwinner,pins = "PC6", "PC7", "PC8", "PC9",
>> +                                              "PC10", "PC11", "PC12",
>> +                                              "PC13", "PC14", "PC15",
>> +                                              "PC24";
>> +                             allwinner,function = "mmc3";
>> +                             allwinner,drive = <SUN4I_PINCTRL_40_MA>;
>> +                             allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> +                     };
>> +
>
> Is that reset pin optional?
>
> If so, I'd prefer it to be a separate node, like we're doing for the
> SPI chip selects for example.
>
> It allows more reusability between different devices without declaring
> new nodes.

All eMMC devices have a reset pin. The MMC standard specifies this as
one way to reset the card, others being a special reset command, or
powering the card off. It also notes a state when the card will not
accept commands, and will require a power cycle or asserting the reset
pin.

I assume all designs would route this pin. The FEX files also have this
pin included by default.


Regards
ChenYu

Re: [PATCH RFC 08/15] ARM: dts: sun6i: Add mmc3 pins for 8 bit emmc

[Maxime Ripard]

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Hi,

On Sat, Jan 23, 2016 at 07:04:54PM +0800, Chen-Yu Tsai wrote:
> Hi,
> 
> On Sat, Jan 23, 2016 at 4:31 AM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > Hi,
> >
> > On Thu, Jan 21, 2016 at 01:26:35PM +0800, Chen-Yu Tsai wrote:
> >> mmc2 and mmc3 are available on the same pins, with different mux values.
> >> However, only mmc3 supports 8 bit DDR transfer modes.
> >>
> >> Since preference for mmc3 over mmc2 is due to DDR transfer modes, just
> >> set the drive strength to 40mA, which is needed for DDR.
> >>
> >> This pinmux setting also includes the hardware reset pin for emmc.
> >>
> >> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> >> ---
> >>  arch/arm/boot/dts/sun6i-a31.dtsi | 10 ++++++++++
> >>  1 file changed, 10 insertions(+)
> >>
> >> diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
> >> index b6ad7850fac6..1867af24ff52 100644
> >> --- a/arch/arm/boot/dts/sun6i-a31.dtsi
> >> +++ b/arch/arm/boot/dts/sun6i-a31.dtsi
> >> @@ -709,6 +709,16 @@
> >>                               allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> >>                       };
> >>
> >> +                     mmc3_8bit_emmc_pins: mmc3@1 {
> >> +                             allwinner,pins = "PC6", "PC7", "PC8", "PC9",
> >> +                                              "PC10", "PC11", "PC12",
> >> +                                              "PC13", "PC14", "PC15",
> >> +                                              "PC24";
> >> +                             allwinner,function = "mmc3";
> >> +                             allwinner,drive = <SUN4I_PINCTRL_40_MA>;
> >> +                             allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> >> +                     };
> >> +
> >
> > Is that reset pin optional?
> >
> > If so, I'd prefer it to be a separate node, like we're doing for the
> > SPI chip selects for example.
> >
> > It allows more reusability between different devices without declaring
> > new nodes.
> 
> All eMMC devices have a reset pin. The MMC standard specifies this as
> one way to reset the card, others being a special reset command, or
> powering the card off. It also notes a state when the card will not
> accept commands, and will require a power cycle or asserting the reset
> pin.
> 
> I assume all designs would route this pin. The FEX files also have this
> pin included by default.

I was more concerned about the case were you'd have a 8bits bus
without an emmc. But I guess that can't happen, since all SD cards are
using a 4 bits width anyway.

I'll apply this patch.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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Re: [PATCH RFC 09/15] ARM: dts: sun6i: sina31s: Switch to mmc3 for onboard eMMC

[Maxime Ripard]

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Hi,

On Sat, Jan 23, 2016 at 12:21:55PM +0800, Chen-Yu Tsai wrote:
> On Sat, Jan 23, 2016 at 4:39 AM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > Hi,
> >
> > On Thu, Jan 21, 2016 at 01:26:36PM +0800, Chen-Yu Tsai wrote:
> >> According to Allwinner, only mmc3 supports 8 bit DDR transfers for eMMC.
> >> Switch to mmc3 for the onboard eMMC, and also assign vqmmc for signal
> >> voltage sensing/switching, and "cap-mmc-hw-reset" to denote this
> >> instance can use eMMC hardware reset.
> >>
> >> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> >> ---
> >>  arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi | 6 ++++--
> >>  1 file changed, 4 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi b/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
> >> index ea69fb8ad4d8..4ec0c8679b2e 100644
> >> --- a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
> >> +++ b/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
> >> @@ -61,12 +61,14 @@
> >>  };
> >>
> >>  /* eMMC on core board */
> >> -&mmc2 {
> >> +&mmc3 {
> >>       pinctrl-names = "default";
> >> -     pinctrl-0 = <&mmc2_8bit_emmc_pins>;
> >> +     pinctrl-0 = <&mmc3_8bit_emmc_pins>;
> >>       vmmc-supply = <&reg_dcdc1>;
> >> +     vqmmc-supply = <&reg_dcdc1>;
> >
> > That seems odd. IIRC the VCC was supposed to be fixed and VCCQ could
> > be either at 1.8 or 3V. Having the same regulator on both would make
> > VCCQ forced to 3.3V, which seems to go against your commit log.
> >
> > What's the catch ? :)
> 
> That is how the board is routed. Which means the only use for
> vqmmc-supply is the driver will know that it can only do 3.3V,
> i.e. voltage sensing.
> 
> It is the reason I requested Olimex to look into this. Allwinner
> reference designs all tie vqmmc directly to 3.3V.
> 
> Actually with the latest driver patches, this is not even needed. To
> make the driver backward compatible, if no vqmmc-supply is given, it
> just assumes 3.3V signaling.

Ok. I've applied this patch and changed the commit log to remove the
voltage switching mention then, since it won't happen.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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Re: [PATCH RFC 10/15] ARM: dts: sun8i: Include SDC2_RST pin in mmc2_8bit_pins

[Maxime Ripard]

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On Thu, Jan 21, 2016 at 01:26:37PM +0800, Chen-Yu Tsai wrote:
> mmc2_8bit_pins is used with eMMC chips, which also have a reset pin.
> The MMC controller also has a reset output that is supported.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

Applied, thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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Re: [PATCH RFC 13/15] ARM: dts: sun9i: Include SDC2_RST pin in mmc2_8bit_pins

[Maxime Ripard]

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On Thu, Jan 21, 2016 at 01:26:40PM +0800, Chen-Yu Tsai wrote:
> mmc2_8bit_pins is used with eMMC chips, which also have a reset pin.
> The MMC controller also has a reset output that is supported.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

Applied, thanks!

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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Re: [PATCH RFC 14/15] ARM: dts: sun9i: a80-optimus: Enable hardware reset and HS-DDR for eMMC

[Maxime Ripard]

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On Thu, Jan 21, 2016 at 01:26:41PM +0800, Chen-Yu Tsai wrote:
> mmc2 has a special pin for eMMC hardware reset, which is controllable
> from the controller. Add the "mmc-cap-hw-reset" property to denote that
> this controller supports this function, and the pins are actually used.
> 
> Also increase the signal drive strength for mmc2 pins, for HS-DDR mode
> support.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

Applied, thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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Re: [PATCH RFC 15/15] ARM: dts: sun9i: cubieboard4: Enable hardware reset and HS-DDR for eMMC

[Maxime Ripard]

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On Thu, Jan 21, 2016 at 01:26:42PM +0800, Chen-Yu Tsai wrote:
> mmc2 has a special pin for eMMC hardware reset, which is controllable
> from the controller. Add the "mmc-cap-hw-reset" property to denote that
> this controller supports this function, and the pins are actually used.
> 
> Also increase the signal drive strength for mmc2 pins, for HS-DDR mode
> support.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

Applied, thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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Re: [PATCH RFC 03/15] mmc: sunxi: Block signal voltage switching (CMD11)

[Ulf Hansson]

On 21 January 2016 at 06:26, Chen-Yu Tsai <wens@csie.org> wrote:
> Allwinner's mmc controller supports signal voltage switching. This is
> supported in code in Allwinner's kernel. However, publicly available
> boards all tie it to a fixed 3.0/3.3V regulator, with options to tie
> it to 1.8V for eMMC on some.
>
> Since Allwinner's kernel is an ancient 3.4, it is hard to say whether
> adapting it's code to a modern mainline kernel would work. Block signal
> voltage switching until someone has proper hardware to implement and
> test this.
>
> This only affects SD UHS-1 modes, as eMMC switches the voltage directly
> without any signaling.
>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
>  drivers/mmc/host/sunxi-mmc.c | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
>
> diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
> index 790f01662b4e..0495ae7da6d6 100644
> --- a/drivers/mmc/host/sunxi-mmc.c
> +++ b/drivers/mmc/host/sunxi-mmc.c
> @@ -816,6 +816,20 @@ static void sunxi_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
>                 }
>         }
>
> +       /*
> +        * TODO Support signal voltage switching
> +        *
> +        * Compared to Allwinner's kernel, recent updates in the mmc core
> +        * mean this should be as easy as setting the flags in cmd_val and
> +        * imask, and waiting for it to finish. However no boards support
> +        * this so this cannot be tested. Block it for now.
> +        */
> +       if (cmd->opcode == SD_SWITCH_VOLTAGE) {
> +               mrq->cmd->error = -EPERM;
> +               mmc_request_done(mmc, mrq);
> +               return;
> +       }

Unless some of the MMC_CAP_UHS* mode is set, this command shouldn't be sent.

So, if you *really* want to protect from this, I think it's better to
clear these caps in the ->probe() function, after mmc_of_parse() has
been called.

> +
>         if (cmd->opcode == MMC_GO_IDLE_STATE) {
>                 cmd_val |= SDXC_SEND_INIT_SEQUENCE;
>                 imask |= SDXC_COMMAND_DONE;
> --
> 2.7.0.rc3
>

Kind regards
Uffe

Re: [PATCH RFC 01/15] mmc: sunxi: Document host init sequence

[Ulf Hansson]

On 21 January 2016 at 06:26, Chen-Yu Tsai <wens@csie.org> wrote:
> sunxi_mmc_init_host() originated from Allwinner kernel sources. The
> magic numbers written to various registers was never documented.
>
> Add comments for values found in Allwinner user manuals.
>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

Thanks, applied for next!

Kind regards
Uffe

> ---
>  drivers/mmc/host/sunxi-mmc.c | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
>
> diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
> index 83de82bceafc..cce5ca540857 100644
> --- a/drivers/mmc/host/sunxi-mmc.c
> +++ b/drivers/mmc/host/sunxi-mmc.c
> @@ -284,16 +284,28 @@ static int sunxi_mmc_init_host(struct mmc_host *mmc)
>         if (sunxi_mmc_reset_host(host))
>                 return -EIO;
>
> +       /*
> +        * Burst 8 transfers, RX trigger level: 7, TX trigger level: 8
> +        *
> +        * TODO: sun9i has a larger FIFO and supports higher trigger values
> +        */
>         mmc_writel(host, REG_FTRGL, 0x20070008);
> +       /* Maximum timeout value */
>         mmc_writel(host, REG_TMOUT, 0xffffffff);
> +       /* Unmask SDIO interrupt if needed */
>         mmc_writel(host, REG_IMASK, host->sdio_imask);
> +       /* Clear all pending interrupts */
>         mmc_writel(host, REG_RINTR, 0xffffffff);
> +       /* Debug register? undocumented */
>         mmc_writel(host, REG_DBGC, 0xdeb);
> +       /* Enable CEATA support */
>         mmc_writel(host, REG_FUNS, SDXC_CEATA_ON);
> +       /* Set DMA descriptor list base address */
>         mmc_writel(host, REG_DLBA, host->sg_dma);
>
>         rval = mmc_readl(host, REG_GCTRL);
>         rval |= SDXC_INTERRUPT_ENABLE_BIT;
> +       /* Undocumented, but found in Allwinner code */
>         rval &= ~SDXC_ACCESS_DONE_DIRECT;
>         mmc_writel(host, REG_GCTRL, rval);
>
> --
> 2.7.0.rc3
>

Re: [PATCH RFC 02/15] mmc: sunxi: Return error on mmc_regulator_set_ocr() fail in .set_ios op

[Ulf Hansson]

On 21 January 2016 at 06:26, Chen-Yu Tsai <wens@csie.org> wrote:
> Let .set_ios() fail if mmc_regulator_set_ocr() fails to enable and set a
> proper voltage for vmmc.
>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

Thanks, applied for next!

Kind regards
Uffe


> ---
>  drivers/mmc/host/sunxi-mmc.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
> index cce5ca540857..790f01662b4e 100644
> --- a/drivers/mmc/host/sunxi-mmc.c
> +++ b/drivers/mmc/host/sunxi-mmc.c
> @@ -711,7 +711,10 @@ static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
>                 break;
>
>         case MMC_POWER_UP:
> -               mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
> +               host->ferror = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
> +                                                    ios->vdd);
> +               if (host->ferror)
> +                       return;
>
>                 host->ferror = sunxi_mmc_init_host(mmc);
>                 if (host->ferror)
> --
> 2.7.0.rc3
>

Re: [PATCH RFC 04/15] mmc: sunxi: Support vqmmc regulator

[Ulf Hansson]

On 21 January 2016 at 06:26, Chen-Yu Tsai <wens@csie.org> wrote:
> eMMC chips require 2 power supplies, vmmc for internal logic, and vqmmc
> for driving output buffers. vqmmc also controls signaling voltage. Most
> boards we've seen use the same regulator for both, nevertheless the 2
> have different usages, and should be set separately.
>
> This patch adds support for vqmmc regulator supply, including voltage
> switching. The MMC core can use this to try different signaling voltages
> for eMMC.
>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

Thanks, applied for next!

Kind regards
Uffe

> ---
>  drivers/mmc/host/sunxi-mmc.c | 31 +++++++++++++++++++++++++++++++
>  1 file changed, 31 insertions(+)
>
> diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
> index 0495ae7da6d6..4bec87458317 100644
> --- a/drivers/mmc/host/sunxi-mmc.c
> +++ b/drivers/mmc/host/sunxi-mmc.c
> @@ -28,6 +28,7 @@
>  #include <linux/dma-mapping.h>
>  #include <linux/slab.h>
>  #include <linux/reset.h>
> +#include <linux/regulator/consumer.h>
>
>  #include <linux/of_address.h>
>  #include <linux/of_gpio.h>
> @@ -256,6 +257,9 @@ struct sunxi_mmc_host {
>         struct mmc_request *mrq;
>         struct mmc_request *manual_stop_mrq;
>         int             ferror;
> +
> +       /* vqmmc */
> +       bool            vqmmc_enabled;
>  };
>
>  static int sunxi_mmc_reset_host(struct sunxi_mmc_host *host)
> @@ -716,6 +720,16 @@ static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
>                 if (host->ferror)
>                         return;
>
> +               if (!IS_ERR(mmc->supply.vqmmc)) {
> +                       host->ferror = regulator_enable(mmc->supply.vqmmc);
> +                       if (host->ferror) {
> +                               dev_err(mmc_dev(mmc),
> +                                       "failed to enable vqmmc\n");
> +                               return;
> +                       }
> +                       host->vqmmc_enabled = true;
> +               }
> +
>                 host->ferror = sunxi_mmc_init_host(mmc);
>                 if (host->ferror)
>                         return;
> @@ -727,6 +741,9 @@ static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
>                 dev_dbg(mmc_dev(mmc), "power off!\n");
>                 sunxi_mmc_reset_host(host);
>                 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
> +               if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled)
> +                       regulator_disable(mmc->supply.vqmmc);
> +               host->vqmmc_enabled = false;
>                 break;
>         }
>
> @@ -758,6 +775,19 @@ static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
>         }
>  }
>
> +static int sunxi_mmc_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)
> +{
> +       /* vqmmc regulator is available */
> +       if (!IS_ERR(mmc->supply.vqmmc))
> +               return mmc_regulator_set_vqmmc(mmc, ios);
> +
> +       /* no vqmmc regulator, assume fixed regulator at 3/3.3V */
> +       if (mmc->ios.signal_voltage == MMC_SIGNAL_VOLTAGE_330)
> +               return 0;
> +
> +       return -EINVAL;
> +}
> +
>  static void sunxi_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
>  {
>         struct sunxi_mmc_host *host = mmc_priv(mmc);
> @@ -923,6 +953,7 @@ static struct mmc_host_ops sunxi_mmc_ops = {
>         .get_ro          = mmc_gpio_get_ro,
>         .get_cd          = mmc_gpio_get_cd,
>         .enable_sdio_irq = sunxi_mmc_enable_sdio_irq,
> +       .start_signal_voltage_switch = sunxi_mmc_volt_switch,
>         .hw_reset        = sunxi_mmc_hw_reset,
>         .card_busy       = sunxi_mmc_card_busy,
>  };
> --
> 2.7.0.rc3
>

Re: [PATCH RFC 03/15] mmc: sunxi: Block signal voltage switching (CMD11)

[Chen-Yu Tsai]

On Fri, Jan 29, 2016 at 6:42 PM, Ulf Hansson <ulf.hansson@linaro.org> wrote:
> On 21 January 2016 at 06:26, Chen-Yu Tsai <wens@csie.org> wrote:
>> Allwinner's mmc controller supports signal voltage switching. This is
>> supported in code in Allwinner's kernel. However, publicly available
>> boards all tie it to a fixed 3.0/3.3V regulator, with options to tie
>> it to 1.8V for eMMC on some.
>>
>> Since Allwinner's kernel is an ancient 3.4, it is hard to say whether
>> adapting it's code to a modern mainline kernel would work. Block signal
>> voltage switching until someone has proper hardware to implement and
>> test this.
>>
>> This only affects SD UHS-1 modes, as eMMC switches the voltage directly
>> without any signaling.
>>
>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>> ---
>>  drivers/mmc/host/sunxi-mmc.c | 14 ++++++++++++++
>>  1 file changed, 14 insertions(+)
>>
>> diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
>> index 790f01662b4e..0495ae7da6d6 100644
>> --- a/drivers/mmc/host/sunxi-mmc.c
>> +++ b/drivers/mmc/host/sunxi-mmc.c
>> @@ -816,6 +816,20 @@ static void sunxi_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
>>                 }
>>         }
>>
>> +       /*
>> +        * TODO Support signal voltage switching
>> +        *
>> +        * Compared to Allwinner's kernel, recent updates in the mmc core
>> +        * mean this should be as easy as setting the flags in cmd_val and
>> +        * imask, and waiting for it to finish. However no boards support
>> +        * this so this cannot be tested. Block it for now.
>> +        */
>> +       if (cmd->opcode == SD_SWITCH_VOLTAGE) {
>> +               mrq->cmd->error = -EPERM;
>> +               mmc_request_done(mmc, mrq);
>> +               return;
>> +       }
>
> Unless some of the MMC_CAP_UHS* mode is set, this command shouldn't be sent.
>
> So, if you *really* want to protect from this, I think it's better to
> clear these caps in the ->probe() function, after mmc_of_parse() has
> been called.

OK. If we need to block these, then we need to block all the other
unsupported caps, which seems excessive and unnecessary. I'll drop
this patch.

Thanks
ChenYu

>
>> +
>>         if (cmd->opcode == MMC_GO_IDLE_STATE) {
>>                 cmd_val |= SDXC_SEND_INIT_SEQUENCE;
>>                 imask |= SDXC_COMMAND_DONE;
>> --
>> 2.7.0.rc3
>>
>
> Kind regards
> Uffe