From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751495AbcBLTd7 (ORCPT ); Fri, 12 Feb 2016 14:33:59 -0500 Received: from mail.skyhub.de ([78.46.96.112]:45814 "EHLO mail.skyhub.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751410AbcBLTd5 (ORCPT ); Fri, 12 Feb 2016 14:33:57 -0500 Date: Fri, 12 Feb 2016 20:33:53 +0100 From: Borislav Petkov To: Paolo Bonzini Cc: Suravee Suthikulpanit , joro@8bytes.org, alex.williamson@redhat.com, gleb@kernel.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, wei@redhat.com, sherry.hurwitz@amd.com, x86-ml Subject: Re: [PART1 RFC 6/9] svm: Add interrupt injection via AVIC Message-ID: <20160212193353.GH4099@pd.tnic> References: <1455285574-27892-1-git-send-email-suravee.suthikulpanit@amd.com> <1455285574-27892-7-git-send-email-suravee.suthikulpanit@amd.com> <20160212141650.GB4504@pd.tnic> <56BE0043.9050701@amd.com> <20160212171406.GF4099@pd.tnic> <56BE229D.6030206@redhat.com> <20160212183048.GG4099@pd.tnic> <56BE2AFB.4000504@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <56BE2AFB.4000504@redhat.com> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Feb 12, 2016 at 07:56:59PM +0100, Paolo Bonzini wrote: > Ok, next examples: MSR_VM_CR and MSR_VM_IGNNE. :) I knew you were going to dig out some. :-) > Are you okay with moving all the SVM MSRs to virtext.h instead? So I would not move any now and cause unnecessary churn. I think it should be enough if we agree on a strategy wrt msr-index.h and then follow it. I think we should do something similar to pci_ids.h. Let me add tip guys to CC. --- diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 552346598dab..75a5bb61d32f 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -1,7 +1,12 @@ #ifndef _ASM_X86_MSR_INDEX_H #define _ASM_X86_MSR_INDEX_H -/* CPU model specific register (MSR) numbers */ +/* + * CPU model specific register (MSR) numbers. + * + * Do not add new entries to this file unless the definitions are shared + * between multiple compilation units. + */ /* x86-64 specific MSRs */ #define MSR_EFER 0xc0000080 /* extended feature register */ -- Regards/Gruss, Boris. ECO tip #101: Trim your mails when you reply.